On Thu, 2023-01-05 at 14:54 +0200, Mika Kahola wrote: > From: Anusha Srivatsa <anusha.srivatsa@xxxxxxxxx> > > Unlike previous platforms that used PORT_TX_DFLEXDPSP > for max_lane calculation, MTL uses only PORT_TX_DFLEXPA1 > from which the max_lanes has to be calculated. "have to be calculated" or "the max_lanes value has..." > Bspec: 50235, 65380 > Cc: Mika Kahola <mika.kahola@xxxxxxxxx> Shouldn't you have an s-o-b instead of Cc, since you rebased it and sent it out? > Cc: Imre Deak <imre.deak@xxxxxxxxx> > Cc: Matt Roper <matthew.d.roper@xxxxxxxxx> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@xxxxxxxxx> > Signed-off-by: Jose Roberto de Souza <jose.souza@xxxxxxxxx> > Link: https://patchwork.freedesktop.org/patch/msgid/20221014124740.774835-21-mika.kahola@xxxxxxxxx > --- > drivers/gpu/drm/i915/display/intel_tc.c | 30 +++++++++++++++++++++++++ > 1 file changed, 30 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c > index de851fddb255..e7d5301fc35e 100644 > --- a/drivers/gpu/drm/i915/display/intel_tc.c > +++ b/drivers/gpu/drm/i915/display/intel_tc.c > @@ -15,6 +15,10 @@ > #include "intel_mg_phy_regs.h" > #include "intel_tc.h" > > +#define DP_PIN_ASSIGNMENT_C 0x3 > +#define DP_PIN_ASSIGNMENT_D 0x4 > +#define DP_PIN_ASSIGNMENT_E 0x5 > + > static const char *tc_port_mode_name(enum tc_port_mode mode) > { > static const char * const names[] = { > @@ -147,6 +151,29 @@ u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port) > DP_PIN_ASSIGNMENT_SHIFT(dig_port->tc_phy_fia_idx); > } > > +static int mtl_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port) This is a bit of a misnomer, since the function doesn't return the pin assignment mask. It returns the max lane count. I suggest mtl_tc_port_get_max_lane_count(), like in the patch I sent internally. ;) -- Cheers, Luca.
