On Tue, Jan 24, 2023 at 05:14:07PM -0800, Matt Roper wrote:
> GAMSTLB_CTRL and GAMCNTRL_CTRL became multicast/replicated registers on
> Xe_HP. They should be defined accordingly and use MCR-aware operations.
>
> These registers have only been used for some dg2/xehpsdv workarounds, so
> this fix is mostly just for consistency/future-proofing; even lacking
> the MCR annotation, workarounds will always be properly applied in a
> multicast manner on these platforms.
>
> Cc: Gustavo Sousa <gustavo.sousa@xxxxxxxxx>
> Fixes: 58bc2453ab8a ("drm/i915: Define multicast registers as a new type")
> Signed-off-by: Matt Roper <matthew.d.roper@xxxxxxxxx>
Reviewed-by: Gustavo Sousa <gustavo.sousa@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 4 ++--
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 16 ++++++++--------
> 2 files changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 4a37d048b512..a0ebf3fa63ca 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -1105,12 +1105,12 @@
> #define VEBX_MOD_CTRL MCR_REG(0xcf38)
> #define FORCE_MISS_FTLB REG_BIT(3)
>
> -#define GEN12_GAMSTLB_CTRL _MMIO(0xcf4c)
> +#define XEHP_GAMSTLB_CTRL MCR_REG(0xcf4c)
> #define CONTROL_BLOCK_CLKGATE_DIS REG_BIT(12)
> #define EGRESS_BLOCK_CLKGATE_DIS REG_BIT(11)
> #define TAG_BLOCK_CLKGATE_DIS REG_BIT(7)
>
> -#define GEN12_GAMCNTRL_CTRL _MMIO(0xcf54)
> +#define XEHP_GAMCNTRL_CTRL MCR_REG(0xcf54)
> #define INVALIDATION_BROADCAST_MODE_DIS REG_BIT(12)
> #define GLOBAL_INVALIDATION_MODE REG_BIT(2)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 0e7f64bb2860..94eb498f3c2c 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1570,8 +1570,8 @@ xehpsdv_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> wa_mcr_write_or(wal, XEHP_MERT_MOD_CTRL, FORCE_MISS_FTLB);
>
> /* Wa_14014368820:xehpsdv */
> - wa_write_or(wal, GEN12_GAMCNTRL_CTRL,
> - INVALIDATION_BROADCAST_MODE_DIS | GLOBAL_INVALIDATION_MODE);
> + wa_mcr_write_or(wal, XEHP_GAMCNTRL_CTRL,
> + INVALIDATION_BROADCAST_MODE_DIS | GLOBAL_INVALIDATION_MODE);
> }
>
> static void
> @@ -1665,10 +1665,10 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> wa_mcr_write_or(wal, SSMCGCTL9530, RTFUNIT_CLKGATE_DIS);
>
> /* Wa_14010680813:dg2_g10 */
> - wa_write_or(wal, GEN12_GAMSTLB_CTRL,
> - CONTROL_BLOCK_CLKGATE_DIS |
> - EGRESS_BLOCK_CLKGATE_DIS |
> - TAG_BLOCK_CLKGATE_DIS);
> + wa_mcr_write_or(wal, XEHP_GAMSTLB_CTRL,
> + CONTROL_BLOCK_CLKGATE_DIS |
> + EGRESS_BLOCK_CLKGATE_DIS |
> + TAG_BLOCK_CLKGATE_DIS);
> }
>
> /* Wa_14014830051:dg2 */
> @@ -1691,8 +1691,8 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> wa_mcr_write_or(wal, VEBX_MOD_CTRL, FORCE_MISS_FTLB);
>
> /* Wa_1509235366:dg2 */
> - wa_write_or(wal, GEN12_GAMCNTRL_CTRL,
> - INVALIDATION_BROADCAST_MODE_DIS | GLOBAL_INVALIDATION_MODE);
> + wa_mcr_write_or(wal, XEHP_GAMCNTRL_CTRL,
> + INVALIDATION_BROADCAST_MODE_DIS | GLOBAL_INVALIDATION_MODE);
> }
>
> static void
> --
> 2.39.0
>
