On Wed, Jan 18, 2023 at 10:51:59AM +0200, Jouni Högander wrote: > Implement Wa_14014971492 and apply it for affected platforms. > > Bspec: 52890, 54369, 55378, 66624 > > Cc: Mika Kahola <mika.kahola@xxxxxxxxx> > Cc: José Roberto de Souza <jose.souza@xxxxxxxxx> > Signed-off-by: Jouni Högander <jouni.hogander@xxxxxxxxx> > --- > drivers/gpu/drm/i915/display/intel_psr.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c > index 7d4a15a283a0..24900a790508 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -1842,6 +1842,11 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, > if (full_update) > goto skip_sel_fetch_set_loop; > > + /* Wa_14014971492 */ > + if ((IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) || > + IS_DISPLAY_VER(dev_priv, 12, 13)) This is not true. This lineage number shows as not needed for most of platforms with the display version 12. you should only have TGL and ADL-P here, besides the MTL one... Which, btw, why we have a MTL_DISPLAY macro instead of using the display version :'( && crtc_state->splitter.enable) > + pipe_clip.y1 = 0; > + > ret = drm_atomic_add_affected_planes(&state->base, &crtc->base); > if (ret) > return ret; > -- > 2.34.1 >
