On Fri, Jan 20, 2023 at 08:13:16AM -0800, Matt Roper wrote:
> On Fri, Jan 20, 2023 at 01:06:15PM -0300, Gustavo Sousa wrote:
> > That register became a multicast register as of Xe_HP and it is
> > currently used only for DG2. Use a proper prefix since there could be
> > usage of the same register for previous platforms in the future, which
> > would require a different definition (i.e. using _MMIO).
>
> It might be worth including a quick note here that this oversight
> doesn't actually cause any functional problems on DG2 because the
> workaround-only usage of the register will still wind up happening in a
> multicast manner regardless. The fix is mostly just for consistency and
> future-proofing the code.
>
> Aside from that,
>
> Reviewed-by: Matt Roper <matthew.d.roper@xxxxxxxxx>
Thanks for the review, Matt! Just sent a v2.
>
> >
> > Signed-off-by: Gustavo Sousa <gustavo.sousa@xxxxxxxxx>
> > Cc: Matt Roper <matthew.d.roper@xxxxxxxxx>
> > Cc: Matthew Atwood <matthew.s.atwood@xxxxxxxxx>
> > Fixes: 468a4e630c7d ("drm/i915/dg2: Introduce Wa_18018764978")
> > ---
> > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 +-
> > drivers/gpu/drm/i915/gt/intel_workarounds.c | 4 ++--
> > 2 files changed, 3 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > index 4a4bab261e66..2727645864db 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > @@ -464,7 +464,7 @@
> > #define GEN8_L3CNTLREG _MMIO(0x7034)
> > #define GEN8_ERRDETBCTRL (1 << 9)
> >
> > -#define PSS_MODE2 _MMIO(0x703c)
> > +#define XEHP_PSS_MODE2 MCR_REG(0x703c)
> > #define SCOREBOARD_STALL_FLUSH_CONTROL REG_BIT(5)
> >
> > #define GEN7_SC_INSTDONE _MMIO(0x7100)
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index 918a271447e2..4efc1a532982 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -793,7 +793,7 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine,
> > /* Wa_18018764978:dg2 */
> > if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_C0, STEP_FOREVER) ||
> > IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915))
> > - wa_masked_en(wal, PSS_MODE2, SCOREBOARD_STALL_FLUSH_CONTROL);
> > + wa_mcr_masked_en(wal, XEHP_PSS_MODE2, SCOREBOARD_STALL_FLUSH_CONTROL);
> >
> > /* Wa_15010599737:dg2 */
> > wa_mcr_masked_en(wal, CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN);
> > @@ -821,7 +821,7 @@ static void mtl_ctx_workarounds_init(struct intel_engine_cs *engine,
> > wa_mcr_masked_en(wal, VFLSKPD, VF_PREFETCH_TLB_DIS);
> >
> > /* Wa_18018764978 */
> > - wa_masked_en(wal, PSS_MODE2, SCOREBOARD_STALL_FLUSH_CONTROL);
> > + wa_mcr_masked_en(wal, XEHP_PSS_MODE2, SCOREBOARD_STALL_FLUSH_CONTROL);
> > }
> >
> > /* Wa_18019271663 */
> > --
> > 2.39.0
> >
>
> --
> Matt Roper
> Graphics Software Engineer
> Linux GPU Platform Enablement
> Intel Corporation
