On Thu, 05 Jan 2023, "Manna, Animesh" <animesh.manna@xxxxxxxxx> wrote:
>> -----Original Message-----
>> From: Intel-gfx <intel-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Ville
>> Syrjala
>> Sent: Friday, December 16, 2022 6:08 AM
>> To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx
>> Subject: [PATCH 11/13] drm/i915/dsb: Add mode DSB opcodes
>>
>> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>>
>> Add all the know DSB instruction opcodes.
>>
>> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>> ---
>> drivers/gpu/drm/i915/display/intel_dsb.c | 8 ++++++++
>> 1 file changed, 8 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
>> b/drivers/gpu/drm/i915/display/intel_dsb.c
>> index 7c593ec84d41..96bc117fd6a0 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dsb.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
>> @@ -67,8 +67,16 @@ struct intel_dsb {
>>
>> /* DSB opcodes. */
>> #define DSB_OPCODE_SHIFT 24
>> +#define DSB_OPCODE_NOOP 0x0
>> #define DSB_OPCODE_MMIO_WRITE 0x1
>> +#define DSB_OPCODE_WAIT_USEC 0x2
>> +#define DSB_OPCODE_WAIT_LINES 0x3
>> +#define DSB_OPCODE_WAIT_VBLANKS 0x4
>> +#define DSB_OPCODE_WAIT_DSL_IN 0x5
>> +#define DSB_OPCODE_WAIT_DSL_OUT 0x6
>> +#define DSB_OPCODE_INTERRUPT 0x7
>> #define DSB_OPCODE_INDEXED_WRITE 0x9
>> +#define DSB_OPCODE_POLL 0xA
>> #define DSB_BYTE_EN 0xF
>> #define DSB_BYTE_EN_SHIFT 20
>> #define DSB_REG_VALUE_MASK 0xfffff
>
> Not sure if we can check-in the above macros without its usage.
It depends on the case. Here, I think we can and we should.
BR,
Jani.
>
> Regards,
> Animesh
>
>> --
>> 2.37.4
>
--
Jani Nikula, Intel Open Source Graphics Center
