On Tue, Jun 25, 2013 at 02:43:57PM +0200, Daniel Vetter wrote: > On Tue, Jun 25, 2013 at 08:15:22AM +0100, Chris Wilson wrote: > > With Haswell the transcoders are a separate bank of registers from the > > pipes (4 transcoders, 3 pipes). In event of an error, we want to be sure > > we have a complete and accurate picture of the machine state, so record > > all the transcoders in addition to all the active pipes. > > > > Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> > > I think we should squash this together with the previous patch and move > the cpu_transcoder->pipe readout logic into intel_error_decode, similarly > to how we already augment the various ring register state with useful > context information. > > I just generally prefer our error state capture code to be as dumb as > possible, with the least amount of trust for our hw/sw state that we can > get away with. I've gone ahead and done this and pushed the frobbed patch to dinq. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
