Use MPLLA for DP2.0 rates 20G and 20G, when ssc is enabled. Signed-off-by: Mika Kahola <mika.kahola@xxxxxxxxx> Link: https://patchwork.freedesktop.org/patch/msgid/20221014124740.774835-14-mika.kahola@xxxxxxxxx --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index 7520f50d4ffc..67e8889aec29 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -2128,8 +2128,12 @@ static void intel_program_port_clock_ctl(struct intel_encoder *encoder, if (!intel_panel_use_ssc(i915)) ssc_enabled = false; - /* TODO: DP2.0 10G and 20G rates enable MPLLA*/ - val |= ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0; + /* DP2.0 10G and 20G rates enable MPLLA*/ + if (crtc_state->port_clock == 1000000 || crtc_state->port_clock == 2000000) { + val |= ssc_enabled ? XELPDP_SSC_ENABLE_PLLA : 0; + } else { + val |= ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0; + } } intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port), -- 2.34.1
