> -----Original Message----- > From: Intel-gfx <intel-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Ville > Syrjala > Sent: Friday, December 16, 2022 6:08 AM > To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx > Subject: [PATCH 03/13] drm/i915/dsb: Align DSB register writes to > 8 bytes > > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > Every DSB instruction has to be 8byte aligned. Make sure that is the case for > the non-indexed register writes as well. > The way this could end up unaligned is we emitted an odd number of > indexed register writes beforehand. > > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> LGTM. Reviewed-by: Animesh Manna <animesh.manna@xxxxxxxxx> > --- > drivers/gpu/drm/i915/display/intel_dsb.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c > b/drivers/gpu/drm/i915/display/intel_dsb.c > index 90a22af30aab..6abfd0fc541a 100644 > --- a/drivers/gpu/drm/i915/display/intel_dsb.c > +++ b/drivers/gpu/drm/i915/display/intel_dsb.c > @@ -172,6 +172,9 @@ void intel_dsb_reg_write(struct intel_dsb *dsb, > return; > } > > + /* Every instruction should be 8 byte aligned. */ > + dsb->free_pos = ALIGN(dsb->free_pos, 2); > + > dsb->ins_start_offset = dsb->free_pos; > buf[dsb->free_pos++] = val; > buf[dsb->free_pos++] = (DSB_OPCODE_MMIO_WRITE << > DSB_OPCODE_SHIFT) | > -- > 2.37.4
