Re: [PATCH v7 2/2] drm/i915/mtl: update scaler source and destination limits for MTL

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On 12/23/2022 7:37 PM, Nautiyal, Ankit K wrote:

On 12/23/2022 6:35 PM, Luca Coelho wrote:
From: Animesh Manna <animesh.manna@xxxxxxxxx>

The max source and destination limits for scalers in MTL have changed.
Use the new values accordingly.

Signed-off-by: José Roberto de Souza <jose.souza@xxxxxxxxx>
Signed-off-by: Animesh Manna <animesh.manna@xxxxxxxxx>
Signed-off-by: Luca Coelho <luciano.coelho@xxxxxxxxx>
---

In v2:
    * No changes;

In v3:
    * Removed stray reviewed-by tag;
    * Added my s-o-b.

In v4:
    * No changes.

In v5:
    * Just resent with a cover letter.

In v6:
    * Now the correct version again (same as v4).

In v7:
    * Update to new MTL limits according to the bspec.


  drivers/gpu/drm/i915/display/skl_scaler.c | 40 ++++++++++++++++++-----
  1 file changed, 32 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c
index d7390067b7d4..01e881293612 100644
--- a/drivers/gpu/drm/i915/display/skl_scaler.c
+++ b/drivers/gpu/drm/i915/display/skl_scaler.c
@@ -87,6 +87,10 @@ static u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_cosited)
  #define ICL_MAX_SRC_H 4096
  #define ICL_MAX_DST_W 5120
  #define ICL_MAX_DST_H 4096
+#define MTL_MAX_SRC_W 4096
+#define MTL_MAX_SRC_H 8192
+#define MTL_MAX_DST_W 8192
+#define MTL_MAX_DST_H 8192
  #define SKL_MIN_YUV_420_SRC_W 16
  #define SKL_MIN_YUV_420_SRC_H 16
  @@ -103,6 +107,8 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
      struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
      const struct drm_display_mode *adjusted_mode =
          &crtc_state->hw.adjusted_mode;
+    int min_src_w, min_src_h, min_dst_w, min_dst_h;
+    int max_src_w, max_src_h, max_dst_w, max_dst_h;
        /*
       * Src coordinates are already rotated by 270 degrees for
@@ -157,15 +163,33 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
          return -EINVAL;
      }
  +    min_src_w = SKL_MIN_SRC_W;
+    min_src_h = SKL_MIN_SRC_H;
+    min_dst_w = SKL_MIN_DST_W;
+    min_dst_h = SKL_MIN_DST_H;
+
+    if (DISPLAY_VER(dev_priv) < 11) {
+        max_src_w = SKL_MAX_SRC_W;
+        max_src_h = SKL_MAX_SRC_H;
+        max_dst_w = SKL_MAX_DST_W;
+        max_dst_h = SKL_MAX_DST_H;
+    } else if (DISPLAY_VER(dev_priv) < 14) {
+        max_src_w = ICL_MAX_SRC_W;
+        max_src_h = ICL_MAX_SRC_H;
+        max_dst_w = ICL_MAX_DST_W;
+        max_dst_h = ICL_MAX_DST_H;

Hi Luca,

Recently there is a change in Bspec:50441 and now for Gen 12 scalers, the MAX_SRC_W is 5120 pixels and MAX_SRC_H is 8192.


Slight correction : this is for both Gen12,and 13.

Regards,

Ankit



MAX_DST_W, and MAX_DST_H are 8192.

As we are refactoring this part, can we include a separate patch for Gen 12 in this series?

Thanks & Regards,

Ankit


+    } else {
+        max_src_w = MTL_MAX_SRC_W;
+        max_src_h = MTL_MAX_SRC_H;
+        max_dst_w = MTL_MAX_DST_W;
+        max_dst_h = MTL_MAX_DST_H;
+    }
+
      /* range checks */
-    if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
-        dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
-        (DISPLAY_VER(dev_priv) >= 11 &&
-         (src_w > ICL_MAX_SRC_W || src_h > ICL_MAX_SRC_H ||
-          dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) ||
-        (DISPLAY_VER(dev_priv) < 11 &&
-         (src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
-          dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H)))    {
+    if (src_w < min_src_w || src_h < min_src_h ||
+        dst_w < min_dst_w || dst_h < min_dst_h ||
+        src_w > max_src_w || src_h > max_src_h ||
+        dst_w > max_dst_w || dst_h > max_dst_h) {
          drm_dbg_kms(&dev_priv->drm,
                  "scaler_user index %u.%u: src %ux%u dst %ux%u "
                  "size is out of scaler range\n",



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