On Wed, Dec 14, 2022 at 11:37:19PM +0100, Andi Shyti wrote:
Hi Rodrigo,
On Tue, Dec 13, 2022 at 01:18:48PM +0000, Vivi, Rodrigo wrote:
On Tue, 2022-12-13 at 00:08 +0100, Andi Shyti wrote:
Hi Rodrigo,
On Mon, Dec 12, 2022 at 11:55:10AM -0500, Rodrigo Vivi wrote:
On Mon, Dec 12, 2022 at 05:13:38PM +0100, Andi Shyti wrote:
From: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
After applying an engine reset, on some platforms like
Jasperlake, we
occasionally detect that the engine state is not cleared until
shortly
after the resume. As we try to resume the engine with volatile
internal
state, the first request fails with a spurious CS event (it looks
like
it reports a lite-restore to the hung context, instead of the
expected
idle->active context switch).
Signed-off-by: Chris Wilson <hris@xxxxxxxxxxxxxxxxxx>
There's a typo in the signature email I'm afraid...
oh yes, I forgot the 'C' :)
you forgot?
who signed it off?
Chris, but as I was copy/pasting SoB's I might have
unintentionally removed the 'c'.
Other than that, have we checked the possibility of using the
driver-initiated-flr bit
instead of this second loop? That should be the right way to
guarantee everything is
cleared on gen11+...
maybe I am misinterpreting it, but is FLR the same as resetting
hardware domains individually?
No, it is bigger than that... almost the PCI FLR with some exceptions:
https://lists.freedesktop.org/archives/intel-gfx/2022-December/313956.html
yes, exactly... I would use FLR feedback if I was performing an
FLR reset. But here I'm not doing that, here I'm simply gating
off some power domains. It happens that those power domains turn
on and off engines making them reset.
is this issue only seeing when this reset is called from the
sanitize functions at probe and resumes?
Or from any kind of gt reset?
I don't remember seeing any reference link to the bug in the patch,
hence I'm assuming this is happening in any kind of gt reset that
ends up in this function.
FLR doesn't have anything to do here, also because if you want to
reset a single engine you go through this function, instead of
resetting the whole GPU with whatever is annexed.
yeap. That might be to extreme depending on the case. But all that
I asked was if we were considering this option since this is the
recommended way of reseting our engines nowadays.
This patch is not fixing the "reset" concept of i915, but it's
fixing a missing feedback that happens in one single platform
when trying to gate on/off a domain.
But it is changing the reset concept and timeouts for all the reset
cases in all the platforms.
Maybe I am completely off track, but I don't see connection with
FLR here.
The point is that if a reset is needed, for any reason,
the recommended way for Jasperlake, and any other newer platforms,
is to use the FLR rather than the engine reset. But we are using
the engine reset, and now twice, rather then attempt the recommended
way.
(besides FLR might not be present in all the platforms)
This issue is also not present in all the platforms and you are still
increasing the loops and delay for all the platforms.
Thanks a lot for your inputs,
have we looked to the Jasperlake workarounds to see if we are missing
anything there that could help us in this case instead of this extreme
approach of randomly increasing timeouts and attempts for all the
platforms?
