On Tue, Dec 20, 2022 at 04:01:05PM +0200, Jani Nikula wrote:
> Due to copy-paste fail, MIPI_BKLT_EN_1 would always use PPS index 1,
> never 0. Fix the sloppiest commit in recent memory.
>
> Fixes: f087cfe6fcff ("drm/i915/dsi: add support for ICL+ native MIPI GPIO sequence")
> Reported-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> Signed-off-by: Jani Nikula <jani.nikula@xxxxxxxxx>
Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
> index 41f025f089d9..2cbc1292ab38 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
> +++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
> @@ -430,7 +430,7 @@ static void icl_native_gpio_set_value(struct drm_i915_private *dev_priv,
> break;
> case MIPI_BKLT_EN_1:
> case MIPI_BKLT_EN_2:
> - index = gpio == MIPI_AVDD_EN_1 ? 0 : 1;
> + index = gpio == MIPI_BKLT_EN_1 ? 0 : 1;
>
> intel_de_rmw(dev_priv, PP_CONTROL(index), EDP_BLC_ENABLE,
> value ? EDP_BLC_ENABLE : 0);
> --
> 2.34.1
--
Ville Syrjälä
Intel
