> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Ville Syrjala
> Sent: Wednesday, November 23, 2022 8:57 PM
> To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> Subject: [PATCH 06/13] drm/i915: Document LUT "max" register precision
>
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> Document the precision of the LUT "max" registers, just so we don't have to dig
> through the spec so much.
Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@xxxxxxxxx>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 22fb9fd78483..cd0a445814c7 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3620,7 +3620,7 @@
>
> #define _PIPEAGCMAX 0x70010
> #define _PIPEBGCMAX 0x71010
> -#define PIPEGCMAX(pipe, i) _MMIO_PIPE2(pipe, _PIPEAGCMAX + (i) * 4)
> +#define PIPEGCMAX(pipe, i) _MMIO_PIPE2(pipe, _PIPEAGCMAX + (i) * 4) /* u1.16
> */
>
> #define _PIPE_ARB_CTL_A 0x70028 /* icl+ */
> #define PIPE_ARB_CTL(pipe) _MMIO_PIPE2(pipe, _PIPE_ARB_CTL_A)
> @@ -5304,7 +5304,7 @@
>
> #define _PREC_PIPEAGCMAX 0x4d000
> #define _PREC_PIPEBGCMAX 0x4d010
> -#define PREC_PIPEGCMAX(pipe, i) _MMIO(_PIPE(pipe, _PIPEAGCMAX,
> _PIPEBGCMAX) + (i) * 4)
> +#define PREC_PIPEGCMAX(pipe, i) _MMIO(_PIPE(pipe, _PIPEAGCMAX,
> _PIPEBGCMAX) + (i) * 4) /* u1.16 */
>
> #define _GAMMA_MODE_A 0x4a480
> #define _GAMMA_MODE_B 0x4ac80
> @@ -7551,9 +7551,9 @@ enum skl_power_gate {
>
> #define PREC_PAL_INDEX(pipe) _MMIO_PIPE(pipe, _PAL_PREC_INDEX_A,
> _PAL_PREC_INDEX_B)
> #define PREC_PAL_DATA(pipe) _MMIO_PIPE(pipe, _PAL_PREC_DATA_A,
> _PAL_PREC_DATA_B)
> -#define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe,
> _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4)
> -#define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe,
> _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4)
> -#define PREC_PAL_EXT2_GC_MAX(pipe, i) _MMIO(_PIPE(pipe,
> _PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_MAX_B) + (i) * 4)
> +#define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe,
> _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4) /* u1.16 */
> +#define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe,
> _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4) /* u3.16 */
> +#define PREC_PAL_EXT2_GC_MAX(pipe, i) _MMIO(_PIPE(pipe,
> _PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_MAX_B) + (i) * 4) /* glk+,
> u3.16 */
>
> #define _PRE_CSC_GAMC_INDEX_A 0x4A484
> #define _PRE_CSC_GAMC_INDEX_B 0x4AC84
> --
> 2.37.4
