On Tue, 22 Nov 2022, Ville Syrjala <ville.syrjala@xxxxxxxxxxxxxxx> wrote: > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > Polish the DVO port regisesters with REG_BIT()/etc. > > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> Reviewed-by: Jani Nikula <jani.nikula@xxxxxxxxx> > --- > drivers/gpu/drm/i915/display/intel_dvo.c | 7 +-- > drivers/gpu/drm/i915/i915_reg.h | 63 +++++++++++++----------- > 2 files changed, 37 insertions(+), 33 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c b/drivers/gpu/drm/i915/display/intel_dvo.c > index b36c3a620250..a5c464c82e5c 100644 > --- a/drivers/gpu/drm/i915/display/intel_dvo.c > +++ b/drivers/gpu/drm/i915/display/intel_dvo.c > @@ -148,7 +148,7 @@ static bool intel_dvo_get_hw_state(struct intel_encoder *encoder, > > tmp = intel_de_read(i915, DVO(port)); > > - *pipe = (tmp & DVO_PIPE_SEL_MASK) >> DVO_PIPE_SEL_SHIFT; > + *pipe = REG_FIELD_GET(DVO_PIPE_SEL_MASK, tmp); > > return tmp & DVO_ENABLE; > } > @@ -291,7 +291,7 @@ static void intel_dvo_pre_enable(struct intel_atomic_state *state, > /* Save the active data order, since I don't know what it should be set to. */ > dvo_val = intel_de_read(i915, DVO(port)) & > (DVO_DEDICATED_INT_ENABLE | > - DVO_PRESERVE_MASK | DVO_ACT_DATA_ORDER_GBRG); > + DVO_PRESERVE_MASK | DVO_ACT_DATA_ORDER_MASK); > dvo_val |= DVO_DATA_ORDER_FP | DVO_BORDER_ENABLE | > DVO_BLANK_ACTIVE_HIGH; > > @@ -303,7 +303,8 @@ static void intel_dvo_pre_enable(struct intel_atomic_state *state, > dvo_val |= DVO_VSYNC_ACTIVE_HIGH; > > intel_de_write(i915, DVO_SRCDIM(port), > - (adjusted_mode->crtc_hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) | (adjusted_mode->crtc_vdisplay << DVO_SRCDIM_VERTICAL_SHIFT)); > + DVO_SRCDIM_HORIZONTAL(adjusted_mode->crtc_hdisplay) | > + DVO_SRCDIM_VERTICAL(adjusted_mode->crtc_vdisplay)); > intel_de_write(i915, DVO(port), dvo_val); > } > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 464be86d6125..08fdc0107212 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -2581,40 +2581,43 @@ > #define _DVOB 0x61140 > #define _DVOC 0x61160 > #define DVO(port) _MMIO_PORT((port), _DVOA, _DVOB) > -#define DVO_ENABLE (1 << 31) > -#define DVO_PIPE_SEL_SHIFT 30 > -#define DVO_PIPE_SEL_MASK (1 << 30) > -#define DVO_PIPE_SEL(pipe) ((pipe) << 30) > -#define DVO_PIPE_STALL_UNUSED (0 << 28) > -#define DVO_PIPE_STALL (1 << 28) > -#define DVO_PIPE_STALL_TV (2 << 28) > -#define DVO_PIPE_STALL_MASK (3 << 28) > -#define DVO_INTERRUPT_SELECT (1 << 27) > -#define DVO_DEDICATED_INT_ENABLE (1 << 26) > -#define DVO_PRESERVE_MASK (0x3 << 24) > -#define DVO_USE_VGA_SYNC (1 << 15) > -#define DVO_DATA_ORDER_I740 (0 << 14) > -#define DVO_DATA_ORDER_FP (1 << 14) > -#define DVO_VSYNC_DISABLE (1 << 11) > -#define DVO_HSYNC_DISABLE (1 << 10) > -#define DVO_VSYNC_TRISTATE (1 << 9) > -#define DVO_HSYNC_TRISTATE (1 << 8) > -#define DVO_BORDER_ENABLE (1 << 7) > -#define DVO_ACT_DATA_ORDER_GBRG (1 << 6) > -#define DVO_ACT_DATA_ORDER_RGGB (0 << 6) > -#define DVO_ACT_DATA_ORDER_GBRG_ERRATA (0 << 6) > -#define DVO_ACT_DATA_ORDER_RGGB_ERRATA (1 << 6) > -#define DVO_VSYNC_ACTIVE_HIGH (1 << 4) > -#define DVO_HSYNC_ACTIVE_HIGH (1 << 3) > -#define DVO_BLANK_ACTIVE_HIGH (1 << 2) > -#define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */ > -#define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */ > +#define DVO_ENABLE REG_BIT(31) > +#define DVO_PIPE_SEL_MASK REG_BIT(30) > +#define DVO_PIPE_SEL(pipe) REG_FIELD_PREP(DVO_PIPE_SEL_MASK, (pipe)) > +#define DVO_PIPE_STALL_MASK REG_GENMASK(29, 28) > +#define DVO_PIPE_STALL_UNUSED REG_FIELD_PREP(DVO_PIPE_STALL_MASK, 0) > +#define DVO_PIPE_STALL REG_FIELD_PREP(DVO_PIPE_STALL_MASK, 1) > +#define DVO_PIPE_STALL_TV REG_FIELD_PREP(DVO_PIPE_STALL_MASK, 2) > +#define DVO_INTERRUPT_SELECT REG_BIT(27) > +#define DVO_DEDICATED_INT_ENABLE REG_BIT(26) > +#define DVO_PRESERVE_MASK REG_GENMASK(25, 24) > +#define DVO_USE_VGA_SYNC REG_BIT(15) > +#define DVO_DATA_ORDER_MASK REG_BIT(14) > +#define DVO_DATA_ORDER_I740 REG_FIELD_PREP(DVO_DATA_ORDER_MASK, 0) > +#define DVO_DATA_ORDER_FP REG_FIELD_PREP(DVO_DATA_ORDER_MASK, 1) > +#define DVO_VSYNC_DISABLE REG_BIT(11) > +#define DVO_HSYNC_DISABLE REG_BIT(10) > +#define DVO_VSYNC_TRISTATE REG_BIT(9) > +#define DVO_HSYNC_TRISTATE REG_BIT(8) > +#define DVO_BORDER_ENABLE REG_BIT(7) > +#define DVO_ACT_DATA_ORDER_MASK REG_BIT(6) > +#define DVO_ACT_DATA_ORDER_RGGB REG_FIELD_PREP(DVO_ACT_DATA_ORDER_MASK, 0) > +#define DVO_ACT_DATA_ORDER_GBRG REG_FIELD_PREP(DVO_ACT_DATA_ORDER_MASK, 1) > +#define DVO_ACT_DATA_ORDER_GBRG_ERRATA REG_FIELD_PREP(DVO_ACT_DATA_ORDER_MASK, 0) > +#define DVO_ACT_DATA_ORDER_RGGB_ERRATA REG_FIELD_PREP(DVO_ACT_DATA_ORDER_MASK, 1) > +#define DVO_VSYNC_ACTIVE_HIGH REG_BIT(4) > +#define DVO_HSYNC_ACTIVE_HIGH REG_BIT(3) > +#define DVO_BLANK_ACTIVE_HIGH REG_BIT(2) > +#define DVO_OUTPUT_CSTATE_PIXELS REG_BIT(1) /* SDG only */ > +#define DVO_OUTPUT_SOURCE_SIZE_PIXELS REG_BIT(0) /* SDG only */ > #define _DVOA_SRCDIM 0x61124 > #define _DVOB_SRCDIM 0x61144 > #define _DVOC_SRCDIM 0x61164 > #define DVO_SRCDIM(port) _MMIO_PORT((port), _DVOA_SRCDIM, _DVOB_SRCDIM) > -#define DVO_SRCDIM_HORIZONTAL_SHIFT 12 > -#define DVO_SRCDIM_VERTICAL_SHIFT 0 > +#define DVO_SRCDIM_HORIZONTAL_MASK REG_GENMASK(22, 12) > +#define DVO_SRCDIM_HORIZONTAL(x) REG_FIELD_PREP(DVO_SRCDIM_HORIZONTAL_MASK, (x)) > +#define DVO_SRCDIM_VERTICAL_MASK REG_GENMASK(10, 0) > +#define DVO_SRCDIM_VERTICAL(x) REG_FIELD_PREP(DVO_SRCDIM_VERTICAL_MASK, (x)) > > /* LVDS port control */ > #define LVDS _MMIO(0x61180) -- Jani Nikula, Intel Open Source Graphics Center
