On Fri, Aug 02, 2013 at 11:48:29AM -0300, Paulo Zanoni wrote:
> 2013/8/1 <ville.syrjala@xxxxxxxxxxxxxxx>:
> > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> >
> > Return UINT_MAX for the calculated WM level if the latency is zero.
> > This will lead to marking the WM level as disabled.
> >
> > I'm not sure if latency==0 should mean that we want to disable the
> > level. But that's the implication I got from the fact that we don't
> > even enable the watermark code of the SSKDP register is 0.
> >
> > v2: Use WARN() to scare people
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> > ---
> > drivers/gpu/drm/i915/intel_pm.c | 6 ++++++
> > 1 file changed, 6 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 53967ef..149eb0a 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -2116,6 +2116,9 @@ static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
> > {
> > uint64_t ret;
> >
> > + if (WARN(latency == 0, "Latency value missing\n"))
>
> I know I'm the person who asked to scream loud in case the latency is
> zero, but I guess that due to the previous patch we'll already
> DRM_ERROR in case the latency is zero, so this WARN will be redundant.
> So maybe your previous patch 16/35 would be more adequate.
>
> So I'll give a "Reviewed-by: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx>"
> to both this and the previous version (16/35), and let you (or Daniel)
> decide which one to merge.
We have a few other cases where we both DRM_ERROR and then WARN into
dmesg, so I'm ok with this one here.
-Daniel
>
>
> > + return UINT_MAX;
> > +
> > ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
> > ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
> >
> > @@ -2128,6 +2131,9 @@ static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
> > {
> > uint32_t ret;
> >
> > + if (WARN(latency == 0, "Latency value missing\n"))
> > + return UINT_MAX;
> > +
> > ret = (latency * pixel_rate) / (pipe_htotal * 10000);
> > ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
> > ret = DIV_ROUND_UP(ret, 64) + 2;
> > --
> > 1.8.1.5
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>
>
> --
> Paulo Zanoni
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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