== Series Details == Series: drm/i915/tgl+: Fix race conditions during DKL PHY accesses (rev5) URL : https://patchwork.freedesktop.org/series/109963/ State : warning == Summary == Error: dim checkpatch failed 15062ed1404b drm/i915/tgl+: Add locking around DKL PHY register accesses Traceback (most recent call last): File "scripts/spdxcheck.py", line 6, in <module> from ply import lex, yacc ModuleNotFoundError: No module named 'ply' Traceback (most recent call last): File "scripts/spdxcheck.py", line 6, in <module> from ply import lex, yacc ModuleNotFoundError: No module named 'ply' -:218: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #218: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 442 lines checked d90f6b228a01 drm/i915: Rename intel_tc_phy_regs.h to intel_mg_phy_regs.h -:51: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #51: rename from drivers/gpu/drm/i915/display/intel_tc_phy_regs.h total: 0 errors, 1 warnings, 0 checks, 48 lines checked 4570d7dd4e54 drm/i915/tgl+: Move DKL PHY register definitions to intel_dkl_phy_regs.h Traceback (most recent call last): File "scripts/spdxcheck.py", line 6, in <module> from ply import lex, yacc ModuleNotFoundError: No module named 'ply' -:57: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #57: new file mode 100644 -:94: WARNING:LONG_LINE: line length of 108 exceeds 100 columns #94: FILE: drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h:33: +#define DKL_PLL_DIV0_AFC_STARTUP(val) REG_FIELD_PREP(DKL_PLL_DIV0_AFC_STARTUP_MASK, (val)) -:199: WARNING:LONG_LINE: line length of 120 exceeds 100 columns #199: FILE: drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h:138: +#define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(val) REG_FIELD_PREP(DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK, (val)) -:201: WARNING:LONG_LINE: line length of 120 exceeds 100 columns #201: FILE: drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h:140: +#define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(val) REG_FIELD_PREP(DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, (val)) total: 0 errors, 4 warnings, 0 checks, 413 lines checked 0b7eb0f5a4e6 drm/i915/tgl+: Sanitize DKL PHY register definitions -:294: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'phy_offset' - possible side-effects? #294: FILE: drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h:39: +#define _DKL_REG(tc_port, phy_offset) \ + ((const struct intel_dkl_phy_reg) { \ + .reg = _DKL_REG_PHY_BASE(tc_port) + \ + _DKL_REG_BANK_OFFSET(phy_offset), \ + .bank_idx = _DKL_REG_BANK_IDX(phy_offset), \ + }) -:301: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'ln0_offs' - possible side-effects? #301: FILE: drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h:46: +#define _DKL_REG_LN(tc_port, ln_idx, ln0_offs, ln1_offs) \ + _DKL_REG(tc_port, (ln0_offs) + (ln_idx) * ((ln1_offs) - (ln0_offs))) total: 0 errors, 0 warnings, 2 checks, 584 lines checked
