Instruction prefetch mechanism requires that 512 bytes after the last command should be readable by EU. Otherwise DMAR errors and engine hangs can happen. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5278 Signed-off-by: Andrzej Hajda <andrzej.hajda@xxxxxxxxx> --- drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c b/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c index 3c55e77b0f1b00..fe999a02f8e10a 100644 --- a/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c +++ b/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c @@ -50,7 +50,7 @@ igt_emit_store_dw(struct i915_vma *vma, u32 *cmd; int err; - size = (4 * count + 1) * sizeof(u32); + size = (4 * count + 1) * sizeof(u32) + 512; size = round_up(size, PAGE_SIZE); obj = i915_gem_object_create_internal(vma->vm->i915, size); if (IS_ERR(obj)) -- 2.34.1
