== Series Details == Series: series starting with [1/3] drm/i915/tgl+: Add locking around DKL PHY register accesses URL : https://patchwork.freedesktop.org/series/109834/ State : warning == Summary == Error: dim checkpatch failed 3b99286d8d78 drm/i915/tgl+: Add locking around DKL PHY register accesses -:160: CHECK:UNCOMMENTED_DEFINITION: spinlock_t definition without comment #160: FILE: drivers/gpu/drm/i915/display/intel_display_core.h:398: + spinlock_t dkl_lock; -:473: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'reg' - possible side-effects? #473: FILE: drivers/gpu/drm/i915/i915_reg.h:7446: +#define DKL_REG_TC_PORT(reg) (((reg).reg - _DKL_PHY1_BASE) >> _DKL_BANK_SHIFT) total: 0 errors, 0 warnings, 2 checks, 405 lines checked a96e4b0b1cb6 drm/i915/tgl+: Move DKL PHY register definitions to intel_tc_phy_regs.h -:51: WARNING:LONG_LINE: line length of 105 exceeds 100 columns #51: FILE: drivers/gpu/drm/i915/display/intel_tc_phy_regs.h:290: +#define DKL_REG_TC_PORT(reg) (((reg).reg - _DKL_PHY1_BASE) >> _DKL_BANK_SHIFT) -:51: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'reg' - possible side-effects? #51: FILE: drivers/gpu/drm/i915/display/intel_tc_phy_regs.h:290: +#define DKL_REG_TC_PORT(reg) (((reg).reg - _DKL_PHY1_BASE) >> _DKL_BANK_SHIFT) -:67: WARNING:LONG_LINE: line length of 108 exceeds 100 columns #67: FILE: drivers/gpu/drm/i915/display/intel_tc_phy_regs.h:306: +#define DKL_PLL_DIV0_AFC_STARTUP(val) REG_FIELD_PREP(DKL_PLL_DIV0_AFC_STARTUP_MASK, (val)) -:172: WARNING:LONG_LINE: line length of 120 exceeds 100 columns #172: FILE: drivers/gpu/drm/i915/display/intel_tc_phy_regs.h:411: +#define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(val) REG_FIELD_PREP(DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK, (val)) -:174: WARNING:LONG_LINE: line length of 120 exceeds 100 columns #174: FILE: drivers/gpu/drm/i915/display/intel_tc_phy_regs.h:413: +#define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(val) REG_FIELD_PREP(DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, (val)) total: 0 errors, 4 warnings, 1 checks, 388 lines checked 003469f884e8 drm/i915/tgl+: Sanitize DKL PHY register definitions -:317: WARNING:LONG_LINE: line length of 101 exceeds 100 columns #317: FILE: drivers/gpu/drm/i915/display/intel_tc.c:960: +void intel_tc_dkl_rmw(struct drm_i915_private *i915, struct intel_tc_dkl_reg reg, u32 clear, u32 set) -:371: WARNING:LONG_LINE: line length of 102 exceeds 100 columns #371: FILE: drivers/gpu/drm/i915/display/intel_tc.h:43: +void intel_tc_dkl_rmw(struct drm_i915_private *i915, struct intel_tc_dkl_reg reg, u32 clear, u32 set); -:403: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'reg' - possible side-effects? #403: FILE: drivers/gpu/drm/i915/display/intel_tc_phy_regs.h:298: +#define DKL_REG_MMIO(reg) _MMIO(reg.reg) -:409: WARNING:LONG_LINE: line length of 101 exceeds 100 columns #409: FILE: drivers/gpu/drm/i915/display/intel_tc_phy_regs.h:304: +#define _DKL_REG_BANK_OFFSET(phy_offset) ((phy_offset) & ((1 << _DKL_BANK_SHIFT) - 1)) -:412: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'phy_offset' - possible side-effects? #412: FILE: drivers/gpu/drm/i915/display/intel_tc_phy_regs.h:307: +#define _DKL_REG(tc_port, phy_offset) \ + ((const struct intel_tc_dkl_reg) { \ + .reg = _DKL_REG_PHY_BASE(tc_port) + \ + _DKL_REG_BANK_OFFSET(phy_offset), \ + .bank_idx = _DKL_REG_BANK_IDX(phy_offset), \ + }) -:419: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'ln0_offs' - possible side-effects? #419: FILE: drivers/gpu/drm/i915/display/intel_tc_phy_regs.h:314: +#define _DKL_REG_LN(tc_port, ln_idx, ln0_offs, ln1_offs) \ + _DKL_REG(tc_port, (ln0_offs) + (ln_idx) * ((ln1_offs) - (ln0_offs))) total: 0 errors, 3 warnings, 3 checks, 578 lines checked
