From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> Rename a few g4x bits to match the ibx+ bits. Cc: Chaitanya Kumar Borah <chaitanya.kumar.borah@xxxxxxxxx> Cc: Kai Vehmanen <kai.vehmanen@xxxxxxxxxxxxxxx> Cc: Takashi Iwai <tiwai@xxxxxxx> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> --- drivers/gpu/drm/i915/display/intel_audio.c | 10 +++++----- drivers/gpu/drm/i915/display/intel_audio_regs.h | 4 ++-- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c index f79efc6e069c..c6f0c8be82b2 100644 --- a/drivers/gpu/drm/i915/display/intel_audio.c +++ b/drivers/gpu/drm/i915/display/intel_audio.c @@ -340,7 +340,7 @@ static void g4x_audio_codec_disable(struct intel_encoder *encoder, /* Invalidate ELD */ tmp = intel_de_read(i915, G4X_AUD_CNTL_ST); - tmp &= ~G4X_ELDV; + tmp &= ~G4X_ELD_VALID; intel_de_write(i915, G4X_AUD_CNTL_ST, tmp); } @@ -355,13 +355,13 @@ static void g4x_audio_codec_enable(struct intel_encoder *encoder, int len, i; if (intel_eld_uptodate(connector, - G4X_AUD_CNTL_ST, G4X_ELDV, - G4X_AUD_CNTL_ST, G4X_ELD_ADDR_MASK, + G4X_AUD_CNTL_ST, G4X_ELD_VALID, + G4X_AUD_CNTL_ST, G4X_ELD_ADDRESS_MASK, G4X_HDMIW_HDMIEDID)) return; tmp = intel_de_read(i915, G4X_AUD_CNTL_ST); - tmp &= ~(G4X_ELDV | G4X_ELD_ADDR_MASK); + tmp &= ~(G4X_ELD_VALID | G4X_ELD_ADDRESS_MASK); len = REG_FIELD_GET(G4X_ELD_BUFFER_SIZE_MASK, tmp); intel_de_write(i915, G4X_AUD_CNTL_ST, tmp); @@ -371,7 +371,7 @@ static void g4x_audio_codec_enable(struct intel_encoder *encoder, *((const u32 *)eld + i)); tmp = intel_de_read(i915, G4X_AUD_CNTL_ST); - tmp |= G4X_ELDV; + tmp |= G4X_ELD_VALID; intel_de_write(i915, G4X_AUD_CNTL_ST, tmp); } diff --git a/drivers/gpu/drm/i915/display/intel_audio_regs.h b/drivers/gpu/drm/i915/display/intel_audio_regs.h index b5684ed839be..4f432c2eb543 100644 --- a/drivers/gpu/drm/i915/display/intel_audio_regs.h +++ b/drivers/gpu/drm/i915/display/intel_audio_regs.h @@ -9,9 +9,9 @@ #include "i915_reg_defs.h" #define G4X_AUD_CNTL_ST _MMIO(0x620B4) -#define G4X_ELDV REG_BIT(14) +#define G4X_ELD_VALID REG_BIT(14) #define G4X_ELD_BUFFER_SIZE_MASK REG_GENMASK(13, 9) -#define G4X_ELD_ADDR_MASK REG_GENMASK(8, 5) +#define G4X_ELD_ADDRESS_MASK REG_GENMASK(8, 5) #define G4X_ELD_ACK REG_BIT(4) #define G4X_HDMIW_HDMIEDID _MMIO(0x6210C) -- 2.35.1
