On 11/10/2022 16:28, Matthew Auld wrote:
On 11/10/2022 16:03, Tvrtko Ursulin wrote:
On 11/10/2022 15:39, Matthew Auld wrote:
Hi,
On 11/10/2022 14:54, Tvrtko Ursulin wrote:
Hi Matt,
On 04/10/2022 14:19, Matthew Auld wrote:
For these types of display buffers, we need to able to CPU access some
part of the backing memory in prepare_plane_clear_colors(). As a
result
we need to ensure we always place in the mappable part of lmem, which
becomes necessary on small-bar systems.
v2(Nirmoy & Ville):
- Add some commentary for why we need to CPU access the buffer.
- Split out the other changes, so we just consider the display
change
here.
v3:
- Handle this in the dpt path.
v4(Ville):
- Drop the intel_fb_rc_ccs_cc_plane() sanity check in
pin_and_fence_fb_obj(), since we can also trigger this on DG1 it
seems.
Fixes: eb1c535f0d69 ("drm/i915: turn on small BAR support")
That one landed in 6.0 - do you want to send this (with
pre-requisite(s)) to stable? Or if not do you want me to send for
6.1 as part of fixes flow? In which case what are the per-requisites?
This one is only for DG2, which is still hidden behind force_probe,
so not too sure if it needs stable? I think the only pre-requisite is
999f45620772 ("drm/i915: allow control over the flags when
migrating"), but again I'm not too sure how much we care about fixes
for platforms hidden behind force_probe? What do you think?
It is certainly not mandatory, but now that cards are about to ship
and reach end users it may be nice to have if not too hard - at least
for 6.1 release candidates. I am not clear on the importance of the
fix to say for sure. Like what goes bang and under what circumstances.
So I do basically defer to someone who knows those answers.
It's important for small-bar DG2 systems, where it will potentially oops
somewhere in the driver without this, so if we want to support DG2 as a
platform in 6.1, then we also need this fix, along with 999f45620772.
Now that you mention an oops I will definitely aim to pull it in. Thanks!
Regards,
Tvrtko
