Hi Nirmoy and Prathap, On Tue, Sep 27, 2022 at 07:13:13PM +0200, Nirmoy Das wrote: > From: Prathap Kumar Valsan <prathap.kumar.valsan@xxxxxxxxx> > > Add flag to pipecontrol instruction to ensure in-flight writes are > flushed to global observation point. Also split the pipecontrol > instruction like we have in gen8. > > References: https://gitlab.freedesktop.org/drm/intel/-/issues/5886 > Signed-off-by: Prathap Kumar Valsan <prathap.kumar.valsan@xxxxxxxxx> > Signed-off-by: Nirmoy Das <nirmoy.das@xxxxxxxxx> Reviewed-by: Andi Shyti <andi.shyti@xxxxxxxxxxxxxxx> Thanks, Andi > --- > drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 29 +++++++++++++++++------- > 1 file changed, 21 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c > index e49fa6fa6aee..31a2fbd8c4a8 100644 > --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c > +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c > @@ -583,6 +583,8 @@ u32 *gen8_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs) > u32 *gen8_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs) > { > cs = gen8_emit_pipe_control(cs, > + PIPE_CONTROL_CS_STALL | > + PIPE_CONTROL_TLB_INVALIDATE | > PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | > PIPE_CONTROL_DEPTH_CACHE_FLUSH | > PIPE_CONTROL_DC_FLUSH_ENABLE, > @@ -600,15 +602,21 @@ u32 *gen8_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs) > > u32 *gen11_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs) > { > + cs = gen8_emit_pipe_control(cs, > + PIPE_CONTROL_CS_STALL | > + PIPE_CONTROL_TLB_INVALIDATE | > + PIPE_CONTROL_TILE_CACHE_FLUSH | > + PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | > + PIPE_CONTROL_DEPTH_CACHE_FLUSH | > + PIPE_CONTROL_DC_FLUSH_ENABLE, > + 0); > + > + /*XXX: Look at gen8_emit_fini_breadcrumb_rcs */ > cs = gen8_emit_ggtt_write_rcs(cs, > rq->fence.seqno, > hwsp_offset(rq), > - PIPE_CONTROL_CS_STALL | > - PIPE_CONTROL_TILE_CACHE_FLUSH | > - PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | > - PIPE_CONTROL_DEPTH_CACHE_FLUSH | > - PIPE_CONTROL_DC_FLUSH_ENABLE | > - PIPE_CONTROL_FLUSH_ENABLE); > + PIPE_CONTROL_FLUSH_ENABLE | > + PIPE_CONTROL_CS_STALL); > > return gen8_emit_fini_breadcrumb_tail(rq, cs); > } > @@ -715,6 +723,7 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs) > { > struct drm_i915_private *i915 = rq->engine->i915; > u32 flags = (PIPE_CONTROL_CS_STALL | > + PIPE_CONTROL_TLB_INVALIDATE | > PIPE_CONTROL_TILE_CACHE_FLUSH | > PIPE_CONTROL_FLUSH_L3 | > PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | > @@ -731,11 +740,15 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs) > else if (rq->engine->class == COMPUTE_CLASS) > flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS; > > + cs = gen12_emit_pipe_control(cs, PIPE_CONTROL0_HDC_PIPELINE_FLUSH, flags, 0); > + > + /*XXX: Look at gen8_emit_fini_breadcrumb_rcs */ > cs = gen12_emit_ggtt_write_rcs(cs, > rq->fence.seqno, > hwsp_offset(rq), > - PIPE_CONTROL0_HDC_PIPELINE_FLUSH, > - flags); > + 0, > + PIPE_CONTROL_FLUSH_ENABLE | > + PIPE_CONTROL_CS_STALL); > > return gen12_emit_fini_breadcrumb_tail(rq, cs); > } > -- > 2.37.3
