On Tue, 27 Sep 2022, "Almahallawy, Khaled" <khaled.almahallawy@xxxxxxxxx> wrote:
> On Mon, 2022-09-26 at 19:48 +0300, Jani Nikula wrote:
>> On Fri, 16 Sep 2022, Khaled Almahallawy <khaled.almahallawy@xxxxxxxxx
>> > wrote:
>> > Bspecs has updated recently to remove the restriction to disable
>> > DDI/Transcoder before setting PHY test pattern. This update is to
>> > address PHY compliance test failures observed on a port with LTTPR.
>> > The issue is that when Transc. is disabled, the main link signals
>> > fed
>> > to LTTPR will be dropped invalidating link training, which will
>> > affect
>> > the quality of the phy test pattern when the transcoder is enabled
>> > again.
>>
>> And how about platforms prior to display 12? The requirement is still
>> there AFAICT.
>
> This restriction is not needed as well for earlier platforms. We are
> able to set PHY patterns without these restrictions using legacy shell
> script solution we used for compliance since SKL and that what we do
> currently for eDP PHY CTS up to RPL.
> Also windows driver doesn't have this restriction on their code for all
> generations.
>
> Simply just setting DP_COMP_CTL will trigger the phy test pattern
> needed.
Sadly bspec disagrees. :(
Anyway, please repost as new thread to get fresh CI results.
BR,
Jani.
>
> Thanks
> Khaled
>>
>
>
>> BR,
>> Jani.
>>
>>
>> > v2: Update commit message (Clint)
>> >
>> > Bspec: 50482
>> > Cc: Imre Deak <imre.deak@xxxxxxxxx>
>> > Cc: Clint Taylor <clinton.a.taylor@xxxxxxxxx>
>> > Cc: Or Cochvi <or.cochvi@xxxxxxxxx>
>> > Tested-by: Khaled Almahallawy <khaled.almahallawy@xxxxxxxxx>
>> > ---
>> > drivers/gpu/drm/i915/display/intel_dp.c | 59 -------------------
>> > ------
>> > 1 file changed, 59 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
>> > b/drivers/gpu/drm/i915/display/intel_dp.c
>> > index c9be61d2348e..2bf323f3f155 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> > @@ -3675,61 +3675,6 @@ static void
>> > intel_dp_phy_pattern_update(struct intel_dp *intel_dp,
>> > }
>> > }
>> >
>> > -static void
>> > -intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp,
>> > - const struct intel_crtc_state
>> > *crtc_state)
>> > -{
>> > - struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>> > - struct drm_device *dev = dig_port->base.base.dev;
>> > - struct drm_i915_private *dev_priv = to_i915(dev);
>> > - struct intel_crtc *crtc = to_intel_crtc(dig_port-
>> > >base.base.crtc);
>> > - enum pipe pipe = crtc->pipe;
>> > - u32 trans_ddi_func_ctl_value, trans_conf_value,
>> > dp_tp_ctl_value;
>> > -
>> > - trans_ddi_func_ctl_value = intel_de_read(dev_priv,
>> > - TRANS_DDI_FUNC_CTL(pip
>> > e));
>> > - trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
>> > - dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
>> > -
>> > - trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE |
>> > - TGL_TRANS_DDI_PORT_MASK);
>> > - trans_conf_value &= ~PIPECONF_ENABLE;
>> > - dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE;
>> > -
>> > - intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
>> > - intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
>> > - trans_ddi_func_ctl_value);
>> > - intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
>> > -}
>> > -
>> > -static void
>> > -intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp,
>> > - const struct intel_crtc_state
>> > *crtc_state)
>> > -{
>> > - struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>> > - struct drm_device *dev = dig_port->base.base.dev;
>> > - struct drm_i915_private *dev_priv = to_i915(dev);
>> > - enum port port = dig_port->base.port;
>> > - struct intel_crtc *crtc = to_intel_crtc(dig_port-
>> > >base.base.crtc);
>> > - enum pipe pipe = crtc->pipe;
>> > - u32 trans_ddi_func_ctl_value, trans_conf_value,
>> > dp_tp_ctl_value;
>> > -
>> > - trans_ddi_func_ctl_value = intel_de_read(dev_priv,
>> > - TRANS_DDI_FUNC_CTL(pip
>> > e));
>> > - trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
>> > - dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
>> > -
>> > - trans_ddi_func_ctl_value |= TRANS_DDI_FUNC_ENABLE |
>> > - TGL_TRANS_DDI_SELECT_PORT(port);
>> > - trans_conf_value |= PIPECONF_ENABLE;
>> > - dp_tp_ctl_value |= DP_TP_CTL_ENABLE;
>> > -
>> > - intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
>> > - intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
>> > - intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
>> > - trans_ddi_func_ctl_value);
>> > -}
>> > -
>> > static void intel_dp_process_phy_request(struct intel_dp
>> > *intel_dp,
>> > const struct intel_crtc_state
>> > *crtc_state)
>> > {
>> > @@ -3748,14 +3693,10 @@ static void
>> > intel_dp_process_phy_request(struct intel_dp *intel_dp,
>> > intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX,
>> > link_status);
>> >
>> > - intel_dp_autotest_phy_ddi_disable(intel_dp, crtc_state);
>> > -
>> > intel_dp_set_signal_levels(intel_dp, crtc_state, DP_PHY_DPRX);
>> >
>> > intel_dp_phy_pattern_update(intel_dp, crtc_state);
>> >
>> > - intel_dp_autotest_phy_ddi_enable(intel_dp, crtc_state);
>> > -
>> > drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
>> > intel_dp->train_set, crtc_state->lane_count);
--
Jani Nikula, Intel Open Source Graphics Center
