In newer hardware, the FBCs are associated with their pipes, so if the pipe is fused off, it means that the FBC is not available either. We already disable FBC A if pipe A is fused off, but the other FBCs were not handled. Currently we only have FBC A and FBC B, but for consistency, add FBC C and D as well and disable them all accordingly, when their respective pipes are fused off. Signed-off-by: Luca Coelho <luciano.coelho@xxxxxxxxx> --- drivers/gpu/drm/i915/display/intel_fbc.h | 2 ++ drivers/gpu/drm/i915/intel_device_info.c | 3 +++ 2 files changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h b/drivers/gpu/drm/i915/display/intel_fbc.h index 4adb98afe6ff..6720ec8ee8a2 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.h +++ b/drivers/gpu/drm/i915/display/intel_fbc.h @@ -20,6 +20,8 @@ struct intel_plane_state; enum intel_fbc_id { INTEL_FBC_A, INTEL_FBC_B, + INTEL_FBC_C, + INTEL_FBC_D, I915_MAX_FBCS, }; diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index 2018eaaa45f5..b45ffa6e9406 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -459,16 +459,19 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) if (dfsm & SKL_DFSM_PIPE_B_DISABLE) { runtime->pipe_mask &= ~BIT(PIPE_B); runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_B); + runtime->fbc_mask &= ~BIT(INTEL_FBC_B); } if (dfsm & SKL_DFSM_PIPE_C_DISABLE) { runtime->pipe_mask &= ~BIT(PIPE_C); runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C); + runtime->fbc_mask &= ~BIT(INTEL_FBC_C); } if (DISPLAY_VER(dev_priv) >= 12 && (dfsm & TGL_DFSM_PIPE_D_DISABLE)) { runtime->pipe_mask &= ~BIT(PIPE_D); runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_D); + runtime->fbc_mask &= ~BIT(INTEL_FBC_D); } if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE) -- 2.37.2