On Thu, Aug 25, 2022 at 06:23:15PM -0400, Rodrigo Vivi wrote:
> We need to inform PCODE of a desired ring frequencies so PCODE update
> the memory frequencies to us. rps->min_freq and rps->max_freq are the
> frequencies used in that request. However they were unset when SLPC was
> enabled and PCODE never updated the memory freq.
>
> Let's at least for now get these freq set up so we can inform PCODE.
>
> Cc: Ashutosh Dixit <ashutosh.dixit@xxxxxxxxx>
> Tested-by: Sushma Venkatesh Reddy <sushma.venkatesh.reddy@xxxxxxxxx>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
As suggested by Sushma:
Fixes: 7ba79a671568 ("drm/i915/guc/slpc: Gate Host RPS when SLPC is enabled")
Cc: <stable@xxxxxxxxxxxxxxx> # v5.15+
> ---
> drivers/gpu/drm/i915/gt/intel_rps.c | 18 +++++++++++++++++-
> 1 file changed, 17 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
> index 8c289a032103..58a82978d5df 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rps.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
> @@ -1128,6 +1128,20 @@ void gen6_rps_get_freq_caps(struct intel_rps *rps, struct intel_rps_freq_caps *c
> }
> }
>
> +static void rps_basic_init_for_slpc(struct intel_rps *rps)
> +{
> + struct intel_rps_freq_caps caps;
> +
> + /*
> + * Even with SLPC we need to initialize at least a basic min and max
> + * frequency so we can inform pcode a desired IA ring frequency in
> + * gen6_update_ring_freq
> + */
> + gen6_rps_get_freq_caps(rps, &caps);
> + rps->min_freq = caps.min_freq;
> + rps->max_freq = caps.rp0_freq;
> +}
> +
> static void gen6_rps_init(struct intel_rps *rps)
> {
> struct drm_i915_private *i915 = rps_to_i915(rps);
> @@ -1970,8 +1984,10 @@ void intel_rps_init(struct intel_rps *rps)
> {
> struct drm_i915_private *i915 = rps_to_i915(rps);
>
> - if (rps_uses_slpc(rps))
> + if (rps_uses_slpc(rps)) {
> + rps_basic_init_for_slpc(rps);
> return;
> + }
>
> if (IS_CHERRYVIEW(i915))
> chv_rps_init(rps);
> --
> 2.37.1
>
