On Wed, Aug 24, 2022 at 02:26:38PM +0300, Joonas Lahtinen wrote: > Quoting Matt Roper (2022-08-02 18:09:16) > > On Mon, Aug 01, 2022 at 02:38:39PM -0700, Harish Chegondi wrote: > > > Bspec: 46052 > > > Reviewed-by: Matt Roper <matthew.d.roper@xxxxxxxxx> > > > Signed-off-by: Harish Chegondi <harish.chegondi@xxxxxxxxx> > > > > Applied to drm-intel-gt-next. Thanks for the patch. > > This patch is completely lacking the commit message. > > That is unacceptable, please make sure there is a proper commit message > for any merged patches going forward. > > Please do explain the patch rationale in this mail thread so it at least > becomes available from the Link: that gets added by DIM when this was > committed. > > Regards, Joonas There isn't really too much to say on this one. For the record, the justification is that we're implementing Wa_1509727124 from the workaround database which simply tells us that we need to program 0xE18C[9] to 1; this patch is just following that guidance from the spec. There's no further information available beyond that. Going forward we'll make sure we put some kind of statement in the commit message body to make it clear that the workaround number and register/bit setting are the only information we have and that this isn't an oversight. Thanks. Matt -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation
