On Thu, Aug 04, 2022 at 03:59:11PM +0530, Ankit Nautiyal wrote: > WA_14014367875 : When Display PHY is configured in continuous > DCC calibration mode, the DCC (duty cycle correction) for the clock > erroneously goes through a state where the DCC code is 0x00 when it is > supposed to be transitioning from 0x10 to 0x0F. This glitch causes a > distortion in the clock, which leads to a bit error. The issue is known > to be causing flickering with eDP HBR3 panels. > > The work around configures the DCC in one-time-update mode. > This mode updates the DCC code one time during training and then > it does not change. This will prevent on-the-fly updates so that the > glitch does not occur. > > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@xxxxxxxxx> > --- > drivers/gpu/drm/i915/display/intel_combo_phy.c | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c > index 64890f39c3cc..1b8bdc47671d 100644 > --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c > +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c > @@ -242,9 +242,10 @@ static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv, > ICL_PORT_TX_DW8_ODCC_CLK_SEL | > ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2); > > + /* WA_14014367875 Set DCC calibration mode to Read once*/ The usual format is 'Wa_<lineage>:<platforms>', so Wa_22012718247:... 'read once' is 'run once' afaics. > ret &= check_phy_reg(dev_priv, phy, ICL_PORT_PCS_DW1_LN(0, phy), > DCC_MODE_SELECT_MASK, > - DCC_MODE_SELECT_CONTINUOSLY); > + ~DCC_MODE_SELECT_MASK); I can see this WA listed only for ADL_P/N/S and TGL (and not for DG2/RKL for instance). ~DCC_MODE_SELECT_MASK should be 0, maybe add a dcc_calibration_mode() that could be used below as well. Could you file a ticket at https://gfxspecs.intel.com/Predator/Home/Index/49291 which specifies this programming explicitly for each platform, but is incorrect now wrt. the above WA? > } > > ret &= icl_verify_procmon_ref_values(dev_priv, phy); > @@ -366,8 +367,9 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv) > intel_de_write(dev_priv, ICL_PORT_TX_DW8_GRP(phy), val); > > val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy)); > + > + /* WA_14014367875 Set DCC calibration mode to Read once*/ > val &= ~DCC_MODE_SELECT_MASK; > - val |= DCC_MODE_SELECT_CONTINUOSLY; > intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val); > } > > -- > 2.25.1 >
