On Thu, Jul 4, 2013 at 3:02 PM, Ben Widawsky <ben at bwidawsk.net> wrote:
> The EDRAM present register isn't really defined in the docs. It just
> says check to see if it's set to 1. So I haven't defined the 1 value not
> knowing what it actually means.
>
> Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
> ---
> drivers/gpu/drm/i915/i915_gem.c | 4 ++--
> drivers/gpu/drm/i915/i915_reg.h | 4 ++++
> 2 files changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 4200c32..edea2cb 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -4153,8 +4153,8 @@ i915_gem_init_hw(struct drm_device *dev)
> if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
> return -EIO;
>
> - if (IS_HASWELL(dev) && (I915_READ(0x120010) == 1))
> - I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000);
> + if (IS_HASWELL(dev) && (I915_READ(HSW_EDRAM_PRESENT) == 1))
> + I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
even though you said doc doesn't define this register please fwd me
the doc... or please explain what is that
sorry about that, but as I said I'm without access :(
>
> if (HAS_PCH_NOP(dev)) {
> u32 temp = I915_READ(GEN7_MSG_CTL);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 9b51be8..a2553ed 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4469,6 +4469,10 @@
> #define GT_FIFO_FREE_ENTRIES 0x120008
> #define GT_FIFO_NUM_RESERVED_ENTRIES 20
>
> +#define HSW_IDICR 0x9008
> +#define IDIHASHMSK(x) (((x) & 0x3f) << 16)
> +#define HSW_EDRAM_PRESENT 0x120010
> +
> #define GEN6_UCGCTL1 0x9400
> # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5)
> # define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7)
> --
> 1.8.3
>
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--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
