Add a description for intel_guc_tlb_invalidation_type enum. Signed-off-by: Mauro Carvalho Chehab <mchehab@xxxxxxxxxx> --- To avoid mailbombing on a large number of people, only mailing lists were C/C on the cover. See [PATCH v2 00/21] at: https://lore.kernel.org/all/cover.1657800199.git.mchehab@xxxxxxxxxx/ drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h index 5c019856a269..e97065c62d28 100644 --- a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h +++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h @@ -187,6 +187,18 @@ enum intel_guc_state_capture_event_status { /* Flush PPC or SMRO caches along with TLB invalidation request */ #define INTEL_GUC_TLB_INVAL_FLUSH_CACHE (1 << 31) +/** + * enum intel_guc_tlb_invalidation_type - type of TLB cache invalidation + * + * @INTEL_GUC_TLB_INVAL_FULL: + * Global TLB invalidation + * @INTEL_GUC_TLB_INVAL_PAGE_SELECTIVE: + * Page-selective TLB cache invalidation + * @INTEL_GUC_TLB_INVAL_PAGE_SELECTIVE_CTX: + * Context-selective TLB cache invalidation + * @INTEL_GUC_TLB_INVAL_GUC: + * Invalidate TLB on GuC itself + */ enum intel_guc_tlb_invalidation_type { INTEL_GUC_TLB_INVAL_FULL = 0x0, INTEL_GUC_TLB_INVAL_PAGE_SELECTIVE = 0x1, -- 2.36.1
