Add documentation for the 3 new members of struct intel_guc that are used to handle TLB cache invalidation logic. Signed-off-by: Mauro Carvalho Chehab <mchehab@xxxxxxxxxx> --- See [PATCH 00/21] at: https://lore.kernel.org/all/cover.1657703926.git.mchehab@xxxxxxxxxx/ drivers/gpu/drm/i915/gt/uc/intel_guc.h | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h index f82a121b0838..73c46d405dc4 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h @@ -76,11 +76,23 @@ struct intel_guc { */ atomic_t outstanding_submission_g2h; - /** @interrupts: pointers to GuC interrupt-managing functions. */ + /** + * @tlb_lookup: TLB cache invalidation lookup table. + */ struct xarray tlb_lookup; + + /** + * @serial_slot: index to the latest allocated element at the + * @tlb_lookup xarray. + */ u32 serial_slot; + + /** + * @next_seqno: next index to be allocated at the @tlb_lookup xarray. + */ u32 next_seqno; + /** @interrupts: pointers to GuC interrupt-managing functions. */ struct { void (*reset)(struct intel_guc *guc); void (*enable)(struct intel_guc *guc); -- 2.36.1
