> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Matt
> Roper
> Sent: Friday, June 10, 2022 4:08 PM
> To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> Subject: [PATCH] drm/i915/pvc: Adjust EU per SS according to
> HAS_ONE_EU_PER_FUSE_BIT()
>
> If we're treating each bit in the EU fuse register as a single EU instead of a
> pair of EUs, then that also cuts the number of potential EUs per subslice in
> half.
>
> Fixes: 5ac342ef84d7 ("drm/i915/pvc: Add SSEU changes")
> Signed-off-by: Matt Roper <matthew.d.roper@xxxxxxxxx>
Reviewed-by: Anusha Srivatsa<anusha.srivatsa@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/gt/intel_sseu.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c
> b/drivers/gpu/drm/i915/gt/intel_sseu.c
> index 7ef75f0d9c9e..c6d3050604c8 100644
> --- a/drivers/gpu/drm/i915/gt/intel_sseu.c
> +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
> @@ -229,7 +229,7 @@ static void xehp_sseu_info_init(struct intel_gt *gt)
> */
> intel_sseu_set_info(sseu, 1,
> 32 * max(num_geometry_regs,
> num_compute_regs),
> - 16);
> + HAS_ONE_EU_PER_FUSE_BIT(gt->i915) ? 8 : 16);
> sseu->has_xehp_dss = 1;
>
> xehp_load_dss_mask(uncore, &sseu->geometry_subslice_mask,
> --
> 2.35.3
