On Tue, 2022-06-14 at 15:22 +0300, Stanislav Lisovskiy wrote:
> We seem to enable PSR2 and selective fetch even if there are no
> active
> planes. That seems to causes FIFO underruns at least for ADLP.
> Those are gone if we don't do that. Just adding simple check
> in intel_psr2_sel_fetch_config_valid seems to do the trick.
We are already disabling PSR intel_psr_pre_plane_update if
active_planes is 0.
We are also checking active_planes in _intel_psr_post_plane_update and
not enabling PSR if it's 0.
So I'm now wondering what sequence this patch is actually changing?
I.e. where PSR is currently enabled/not disabled if active_planes == 0?
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 7d61c55184e5..03add69cfdca 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -747,6 +747,12 @@ static bool
> intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
> return false;
> }
>
> + if (hweight32(crtc_state->active_planes) == 0) {
> + drm_dbg_kms(&dev_priv->drm,
> + "PSR2 sel fetch not enabled, no
> active_planes\n");
> + return false;
> + }
> +
> /* Wa_14010254185 Wa_14010103792 */
> if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) {
> drm_dbg_kms(&dev_priv->drm,
