Re: [PATCH] drm/i915/dg2: Support 4k@30 on HDMI

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On 5/21/2022 12:50 AM, Matt Roper wrote:
On Wed, May 11, 2022 at 02:01:21PM +0530, Ankit Nautiyal wrote:
From: Vandita Kulkarni <vandita.kulkarni@xxxxxxxxx>

This patch adds a fix to support 297MHz of dot clock by calculating
the pll values using synopsis algorithm.
This will help to support 4k@30 mode for HDMI monitors on DG2.

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@xxxxxxxxx>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@xxxxxxxxx>
---
  drivers/gpu/drm/i915/display/intel_snps_phy.c | 31 +++++++++++++++++++
  1 file changed, 31 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c
index 0dd4775e8195..ec1700dd3bc6 100644
--- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
@@ -517,6 +517,36 @@ static const struct intel_mpllb_state dg2_hdmi_148_5 = {
  		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
  };
+/* values in the below table are calculted using the algo */
+static const struct intel_mpllb_state dg2_hdmi_297 = {
+	.clock = 297000,
+	.ref_control =
+		REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
+	.mpllb_cp =
+		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
+		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
+		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
+		REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
+	.mpllb_div =
+		REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
+		REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
+		REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
+		REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
When I calculate these tables out by hand, I also have

         REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3)

as part of mpllb_div.  Can you double check that?


Thanks Matt, for catching this.

I did find out that the dp_mpllb_freq_vco should be set to 3 for SNPS_PHY_MPLLB_DIV, as per the calculations for 297 Mhz.

I will fix this in the next patch set.

Thanks & Regards,

Ankit



Matt

+	.mpllb_div2 =
+		REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
+		REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) |
+		REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
+	.mpllb_fracn1 =
+		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
+		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
+		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
+	.mpllb_fracn2 =
+		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
+		REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 26214),
+	.mpllb_sscen =
+		REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
+};
+
  static const struct intel_mpllb_state dg2_hdmi_594 = {
  	.clock = 594000,
  	.ref_control =
@@ -551,6 +581,7 @@ static const struct intel_mpllb_state * const dg2_hdmi_tables[] = {
  	&dg2_hdmi_27_0,
  	&dg2_hdmi_74_25,
  	&dg2_hdmi_148_5,
+	&dg2_hdmi_297,
  	&dg2_hdmi_594,
  	NULL,
  };
--
2.25.1




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