On Wed, May 04, 2022 at 12:07:50PM -0700, José Roberto de Souza wrote:
> No need to have this parameter in intel_device_info struct
> as all platforms with graphics version 7 or newer can reset engines.
>
> Signed-off-by: José Roberto de Souza <jose.souza@xxxxxxxxx>
Reviewed-by: Matt Roper <matthew.d.roper@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/gt/intel_reset.c | 2 +-
> drivers/gpu/drm/i915/i915_pci.c | 5 -----
> drivers/gpu/drm/i915/intel_device_info.h | 1 -
> 3 files changed, 1 insertion(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
> index 5422a3b84bd44..894f17f8b4cea 100644
> --- a/drivers/gpu/drm/i915/gt/intel_reset.c
> +++ b/drivers/gpu/drm/i915/gt/intel_reset.c
> @@ -699,7 +699,7 @@ bool intel_has_reset_engine(const struct intel_gt *gt)
> if (gt->i915->params.reset < 2)
> return false;
>
> - return INTEL_INFO(gt->i915)->has_reset_engine;
> + return GRAPHICS_VER(gt->i915) >= 7;
> }
>
> int intel_reset_guc(struct intel_gt *gt)
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 516f28d4db611..b47f8b1ab9c6c 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -454,7 +454,6 @@ static const struct intel_device_info snb_m_gt2_info = {
> .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
> .has_coherent_ggtt = true, \
> .has_llc = 1, \
> - .has_reset_engine = true, \
> .has_rps = true, \
> .dma_mask_size = 40, \
> .ppgtt_type = INTEL_PPGTT_ALIASING, \
> @@ -512,7 +511,6 @@ static const struct intel_device_info vlv_info = {
> .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
> .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
> .has_runtime_pm = 1,
> - .has_reset_engine = true,
> .has_rps = true,
> .display.has_gmch = 1,
> .display.has_hotplug = 1,
> @@ -615,7 +613,6 @@ static const struct intel_device_info chv_info = {
> .dma_mask_size = 39,
> .ppgtt_type = INTEL_PPGTT_FULL,
> .ppgtt_size = 32,
> - .has_reset_engine = 1,
> .has_snoop = true,
> .has_coherent_ggtt = false,
> .display_mmio_offset = VLV_DISPLAY_BASE,
> @@ -696,7 +693,6 @@ static const struct intel_device_info skl_gt4_info = {
> .dma_mask_size = 39, \
> .ppgtt_type = INTEL_PPGTT_FULL, \
> .ppgtt_size = 48, \
> - .has_reset_engine = 1, \
> .has_snoop = true, \
> .has_coherent_ggtt = false, \
> HSW_PIPE_OFFSETS, \
> @@ -995,7 +991,6 @@ static const struct intel_device_info adl_p_info = {
> .has_logical_ring_contexts = 1, \
> .has_logical_ring_elsq = 1, \
> .has_mslices = 1, \
> - .has_reset_engine = 1, \
> .has_rps = 1, \
> .has_runtime_pm = 1, \
> .ppgtt_size = 48, \
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 599cb265946b8..62c9616ea6a9c 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -142,7 +142,6 @@ enum intel_ppgtt_type {
> func(has_64k_pages); \
> func(needs_compact_pt); \
> func(gpu_reset_clobbers_display); \
> - func(has_reset_engine); \
> func(has_4tile); \
> func(has_flat_ccs); \
> func(has_global_mocs); \
> --
> 2.36.0
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
