The series is Reviewed-by: Nirmoy Das <nirmoy.das@xxxxxxxxx>
On 5/4/2022 5:08 PM, Matthew Auld wrote:
Test should still be valid, even if we can't explicitly control the PTE
caching bits, like on discrete, where the caching should already be
enabled by default for system memory objects.
References: https://gitlab.freedesktop.org/drm/intel/-/issues/4873
Signed-off-by: Matthew Auld <matthew.auld@xxxxxxxxx>
Cc: Nirmoy Das <nirmoy.das@xxxxxxxxxxxxxxx>
---
tests/i915/gem_caching.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/tests/i915/gem_caching.c b/tests/i915/gem_caching.c
index 4e844952..eb0170ab 100644
--- a/tests/i915/gem_caching.c
+++ b/tests/i915/gem_caching.c
@@ -147,7 +147,8 @@ igt_main
igt_require_gem(data.fd);
gem_require_blitter(data.fd);
- gem_require_caching(data.fd);
+ if (!gem_has_lmem(data.fd))
+ gem_require_caching(data.fd);
data.devid = intel_get_drm_devid(data.fd);
if (IS_GEN2(data.devid)) /* chipset only handles cached -> uncached */
@@ -162,7 +163,8 @@ igt_main
scratch_buf = intel_buf_create(data.bops, BO_SIZE/4, 1,
32, 0, I915_TILING_NONE, 0);
- gem_set_caching(data.fd, scratch_buf->handle, 1);
+ if (!gem_has_lmem(data.fd))
+ gem_set_caching(data.fd, scratch_buf->handle, 1);
staging_buf = intel_buf_create(data.bops, BO_SIZE/4, 1,
32, 0, I915_TILING_NONE, 0);
