On Mon, 25 Apr 2022 at 16:22, Ramalingam C <ramalingam.c@xxxxxxxxx> wrote: > > From: Akeem G Abodunrin <akeem.g.abodunrin@xxxxxxxxx> > > When bit 19 of MI_LOAD_REGISTER_IMM instruction opcode is set on tgl+ > devices, HW does not care about certain register address offsets, but > instead check the following for valid address ranges on specific engines: > RCS && CCS: BITS(0 - 10) > BCS: BITS(0 - 11) > VECS && VCS: BITS(0 - 13) > Also, tgl+ now support relative addressing for BCS engine - So, this > patch fixes issue with live_gt_lrc selftest that is failing where there is > mismatch between LRC register layout generated during init and HW > default register offsets. > > Signed-off-by: Akeem G Abodunrin <akeem.g.abodunrin@xxxxxxxxx> > cc: Prathap Kumar Valsan <prathap.kumar.valsan@xxxxxxxxx> > Signed-off-by: Ramalingam C <ramalingam.c@xxxxxxxxx> Reviewed-by: Matthew Auld <matthew.auld@xxxxxxxxx>
