From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> Start reordering when we do the clock/dpll calculations during the atomic check. The eventual goals are: - back feed the actually calculated clock into the crtc state so that stuff that depends on it (eg. watermarks) will be calculated based on the actual hardware state we're going to use rather than the semi-fictional state we started with - fix the fastset/fastboot stuff to actually require exact clock matches. Avoids the current mess where the user asks to slightly change the refresh rate (eg. to match video frame rate) but the kernel decides to ignore it and do a fastset instead. v2: Repost of the remainder, earlier patches already merged Ville Syrjälä (4): drm/i915: Split shared dpll .get_dplls() into compute and get phases drm/i915: Do .crtc_compute_clock() earlier drm/i915: Clean up DPLL related debugs drm/i915: Reassign DPLLs only for crtcs going throug .compute_config() drivers/gpu/drm/i915/display/intel_display.c | 26 +- drivers/gpu/drm/i915/display/intel_dpll.c | 98 +++--- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 333 ++++++++++++------ drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 3 + 4 files changed, 275 insertions(+), 185 deletions(-) -- 2.35.1
