== Series Details == Series: drm/i915: Start reordering modeset clock calculations (rev5) URL : https://patchwork.freedesktop.org/series/101789/ State : warning == Summary == Error: dim checkpatch failed 32e8671c097f drm/i915: Make .get_dplls() return int d501feb0cac1 drm/i915: Pass dev_priv to intel_shared_dpll_init() 695e9aa8b693 drm/i915: Remove pointless dpll_funcs checks bfaac2c12523 drm/i915: Adjust .crtc_compute_clock() calling convention 88dbf174e03e drm/i915: Move stuff into intel_dpll_crtc_compute_clock() 51418ba48534 drm/i915: Move the dpll_hw_state clearing to intel_dpll_crtc_compute_clock() a25f16fe3e1c drm/i915: Clear the dpll_hw_state when disabling a pipe d644f564dffe drm/i915: Split out dg2_crtc_compute_clock() 18d0698dce4c drm/i915: Add crtc .crtc_get_shared_dpll() 1545f8bc7636 drm/i915: Split shared dpll .get_dplls() into compute and get phases -:191: CHECK:CAMELCASE: Avoid CamelCase: <SPLL_FREQ_1350MHz> #191: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:1063: + SPLL_PLL_ENABLE | SPLL_FREQ_1350MHz | SPLL_REF_MUXED_SSC; total: 0 errors, 0 warnings, 1 checks, 516 lines checked 7cd29893d822 drm/i915: Do .crtc_compute_clock() earlier 8d6be41a83c2 drm/i915: Clean up DPLL related debugs 2bfb6a621728 drm/i915: Reassign DPLLs only for crtcs going throug .compute_config()
