On Sun, Apr 17, 2022 at 12:31:05PM +0300, Vinod Govindapillai wrote: > In configurations with single DRAM channel, for usecases like > 4K 60 Hz, FIFO underruns are observed quite frequently. Looks > like the wm0 watermark values need to bumped up because the wm0 > memory latency calculations are probably not taking the DRAM > channel's impact into account. > > As per the Bspec 49325, if the ddb allocation can hold at least > one plane_blocks_per_line we should have selected method2. > Assuming that modern HW versions have enough dbuf to hold > at least one line, set the wm blocks to equivalent to blocks > per line. > > v2: styling and comments changes (Ville) > v3: Updated the reviewed-by tag > v4: max_t to max and patch styling (Ville) > > References: https://gitlab.freedesktop.org/drm/intel/-/issues/4321 > Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > Cc: Stanislav Lisovskiy <stanislav.lisovskiy@xxxxxxxxx> > Signed-off-by: Vinod Govindapillai <vinod.govindapillai@xxxxxxxxx> > Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@xxxxxxxxx> Thanks. Pushed to drm-intel-next. > --- > drivers/gpu/drm/i915/intel_pm.c | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 594ab59e4991..ee0047fdc95d 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -5475,6 +5475,25 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state, > } > > blocks = fixed16_to_u32_round_up(selected_result) + 1; > + /* > + * Lets have blocks at minimum equivalent to plane_blocks_per_line > + * as there will be at minimum one line for lines configuration. This > + * is a work around for FIFO underruns observed with resolutions like > + * 4k 60 Hz in single channel DRAM configurations. > + * > + * As per the Bspec 49325, if the ddb allocation can hold at least > + * one plane_blocks_per_line, we should have selected method2 in > + * the above logic. Assuming that modern versions have enough dbuf > + * and method2 guarantees blocks equivalent to at least 1 line, > + * select the blocks as plane_blocks_per_line. > + * > + * TODO: Revisit the logic when we have better understanding on DRAM > + * channels' impact on the level 0 memory latency and the relevant > + * wm calculations. > + */ > + if (skl_wm_has_lines(dev_priv, level)) > + blocks = max(blocks, > + fixed16_to_u32_round_up(wp->plane_blocks_per_line)); > lines = div_round_up_fixed16(selected_result, > wp->plane_blocks_per_line); > > -- > 2.25.1 -- Ville Syrjälä Intel
