Op 07-04-2022 om 15:37 schreef Juha-Pekka Heikkila:
> Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@xxxxxxxxx>
>
> On 4.4.2022 16.38, Imre Deak wrote:
>> From: Mika Kahola <mika.kahola@xxxxxxxxx>
>>
>> DG2 clear color render compression uses Tile4 layout. Therefore, we need
>> to define a new format modifier for uAPI to support clear color rendering.
>>
>> v2:
>> Display version is fixed. [Imre]
>> KDoc is enhanced for cc modifier. [Nanley & Lionel]
>> v3:
>> Split out the modifier addition to a separate patch.
>> Clarify the modifier layout description.
>>
>> Cc: dri-devel@xxxxxxxxxxxxxxxxxxxxx
>> Signed-off-by: Mika Kahola <mika.kahola@xxxxxxxxx>
>> cc: Anshuman Gupta <anshuman.gupta@xxxxxxxxx>
>> Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@xxxxxxxxx>
>> Signed-off-by: Ramalingam C <ramalingam.c@xxxxxxxxx>
>> Signed-off-by: Imre Deak <imre.deak@xxxxxxxxx>
>> Acked-by: Nanley Chery <nanley.g.chery@xxxxxxxxx>
>> ---
>> include/uapi/drm/drm_fourcc.h | 14 ++++++++++++++
>> 1 file changed, 14 insertions(+)
>>
>> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
>> index 4a5117715db3c..e5074162bcdd4 100644
>> --- a/include/uapi/drm/drm_fourcc.h
>> +++ b/include/uapi/drm/drm_fourcc.h
>> @@ -605,6 +605,20 @@ extern "C" {
>> */
>> #define I915_FORMAT_MOD_4_TILED_DG2_MC_CCS fourcc_mod_code(INTEL, 11)
>> +/*
>> + * Intel Color Control Surface with Clear Color (CCS) for DG2 render compression.
>> + *
>> + * The main surface is Tile 4 and at plane index 0. The CCS data is stored
>> + * outside of the GEM object in a reserved memory area dedicated for the
>> + * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The
>> + * main surface pitch is required to be a multiple of four Tile 4 widths. The
>> + * clear color is stored at plane index 1 and the pitch should be ignored. The
>> + * format of the 256 bits of clear color data matches the one used for the
>> + * I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC modifier, see its description
>> + * for details.
>> + */
>> +#define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC fourcc_mod_code(INTEL, 12)
>> +
>> /*
>> * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
>> *
>
I personally think it's not required since it's a i915 only format), but for merging series through drm-intel:
Acked-by: Maarten Lankhorst <maarten.lankhorst@xxxxxxxxxxxxxxx>
