On Thu, Apr 07, 2022 at 02:24:17PM +0300, Lisovskiy, Stanislav wrote: > On Thu, Apr 07, 2022 at 02:10:52PM +0300, Ville Syrjälä wrote: > > On Thu, Apr 07, 2022 at 11:42:35AM +0300, Stanislav Lisovskiy wrote: > > > We had some FIFO underruns appearing on platforms like ADL, > > > which could be fixed though by increasing CDCLK, however we were > > > lacking explanation for that - we were not calculating CDCLK, > > > also based on cumulative bpp W/A formula, mentioned in BSpec 64631. > > > > We already have that in intel_bw_crtc_min_cdclk(). > > It actually is not quite what BSpec is talking about it adds > data_rate per plane, instead of bpp, I think it confuses > those 2 from BSpec: > > " > Plane required bandwidth MB/s = pixel rate MHz * source pixel format in bytes > * plane down scale amount * pipe down scale amount > Display required memory bandwidth MB/s += Plane required bandwidth > Pipe cumulative bytes per pixel += plane source pixel format in bytes > " > > then we have to different formulas used to estimate whats the CDCLK > should be, one is "DBUF maximum data buffer bandwidth MB/s = CDCLK frequency MHz * 64 Bytes" > > another is pipe CDCLK = cumulative bytes per pixel * (pixel rate MHz * > plane down scale amount * pipe down scale amount)) * 51.2) That specific statement in the spec is kinda nonsense. Mixing "plane up/down scale amount" (which is per plane) with this "cumulative bytes per pixel" thing (which is sum of bytes per pixel across all planes) doesn't make sense. What we so is sum bytes_per_pixel*pixel_rate*plane_up/down_scale from all planes, which I think is what the spec is trying to say as that is the cumulative bw used up by all the planes. -- Ville Syrjälä Intel
