On Fri, 2022-04-01 at 15:29 -0700, José Roberto de Souza wrote:
> Following up what was done in commit 804f46885317 ("drm/i915/psr: Set
> "SF Partial Frame Enable" also on full update") and also setting
> partial frame enable when psr_force_hw_tracking_exit() is called.
>
> Also as PSR2_MAN_TRK_CTL is a double buffered registers do a RMW
> is not a good idea so here also setting the man_trk_ctl_enable_bit()
> that is required in TGL and only doing a register write.
Reviewed-by: Jouni Högander <jouni.hogander@xxxxxxxxx>
>
> v2:
> - not doing a rmw
>
> Cc: Jouni Högander <jouni.hogander@xxxxxxxxx>
> Cc: Mika Kahola <mika.kahola@xxxxxxxxx>
> Signed-off-by: José Roberto de Souza <jose.souza@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 18 +++++++++++-------
> 1 file changed, 11 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 80002ca6a6ebe..2da2468f555ec 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1436,6 +1436,11 @@ void intel_psr_resume(struct intel_dp
> *intel_dp)
> mutex_unlock(&psr->lock);
> }
>
> +static inline u32 man_trk_ctl_enable_bit_get(struct drm_i915_private
> *dev_priv)
> +{
> + return IS_ALDERLAKE_P(dev_priv) ? 0 : PSR2_MAN_TRK_CTL_ENABLE;
> +}
> +
> static inline u32 man_trk_ctl_single_full_frame_bit_get(struct
> drm_i915_private *dev_priv)
> {
> return IS_ALDERLAKE_P(dev_priv) ?
> @@ -1455,9 +1460,11 @@ static void psr_force_hw_tracking_exit(struct
> intel_dp *intel_dp)
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>
> if (intel_dp->psr.psr2_sel_fetch_enabled)
> - intel_de_rmw(dev_priv,
> - PSR2_MAN_TRK_CTL(intel_dp-
> >psr.transcoder), 0,
> - man_trk_ctl_single_full_frame_bit_get(dev_
> priv));
> + intel_de_write(dev_priv,
> + PSR2_MAN_TRK_CTL(intel_dp-
> >psr.transcoder),
> + man_trk_ctl_enable_bit_get(dev_priv) |
> + man_trk_ctl_partial_frame_bit_get(dev_pr
> iv) |
> + man_trk_ctl_single_full_frame_bit_get(de
> v_priv));
>
> /*
> * Display WA #0884: skl+
> @@ -1554,10 +1561,7 @@ static void psr2_man_trk_ctl_calc(struct
> intel_crtc_state *crtc_state,
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> - u32 val = 0;
> -
> - if (!IS_ALDERLAKE_P(dev_priv))
> - val = PSR2_MAN_TRK_CTL_ENABLE;
> + u32 val = man_trk_ctl_enable_bit_get(dev_priv);
>
> /* SF partial frame enable has to be set even on full update */
> val |= man_trk_ctl_partial_frame_bit_get(dev_priv);
