== Series Details == Series: i915: Explicit handling of multicast registers (rev2) URL : https://patchwork.freedesktop.org/series/101992/ State : warning == Summary == $ dim checkpatch origin/drm-tip 4e9aab13ef6f drm/i915/gen8: Create separate reg definitions for new MCR registers -:263: WARNING:LONG_LINE: line length of 103 exceeds 100 columns #263: FILE: drivers/gpu/drm/i915/intel_pm.c:7420: + intel_uncore_write(&dev_priv->uncore, GEN8_MISCCPCTL, misccpctl & ~GEN8_DOP_CLOCK_GATE_ENABLE); -:282: WARNING:LONG_LINE: line length of 116 exceeds 100 columns #282: FILE: drivers/gpu/drm/i915/intel_pm.c:7582: + intel_uncore_write(&dev_priv->uncore, GEN8_MISCCPCTL, intel_uncore_read(&dev_priv->uncore, GEN8_MISCCPCTL) & total: 0 errors, 2 warnings, 0 checks, 209 lines checked 960e8b069a70 drm/i915/xehp: Create separate reg definitions for new MCR registers 1f402e414e12 drm/i915/gt: Drop a few unused register definitions e01b2ee254ba drm/i915/gt: Correct prefix on a few registers 6513044bf45f drm/i915/xehp: Check for faults on all mslices b49713c5b6f0 drm/i915: Drop duplicated definition of XEHPSDV_FLAT_CCS_BASE_ADDR 8761ebb0b0f7 drm/i915: Move XEHPSDV_TILE0_ADDR_RANGE to GT register header 4a259d727d7c drm/i915: Define MCR registers explicitly -:149: WARNING:LONG_LINE_COMMENT: line length of 102 exceeds 100 columns #149: FILE: drivers/gpu/drm/i915/gt/intel_gt_regs.h:896: +#define XEHP_LNCFCMOCS(i) MCR_REG(0xb020 + (i) * 4) /* L3 Cache Control */ total: 0 errors, 1 warnings, 0 checks, 327 lines checked b86b7d1f9eed drm/i915/gt: Move multicast register handling to a dedicated file -:386: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #386: new file mode 100644 -:541: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided #541: FILE: drivers/gpu/drm/i915/gt/intel_gt_mcr.c:151: + old_mcr = mcr = intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR); -:608: CHECK:LINE_SPACING: Please don't use multiple blank lines #608: FILE: drivers/gpu/drm/i915/gt/intel_gt_mcr.c:218: + + total: 0 errors, 1 warnings, 2 checks, 937 lines checked f210d9f6bb0d drm/i915/gt: Cleanup interface for MCR operations -:294: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #294: FILE: drivers/gpu/drm/i915/gt/intel_gt_mcr.c:241: +void intel_gt_mcr_multicast_write(struct intel_gt *gt, + i915_reg_t reg, u32 value) -:313: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #313: FILE: drivers/gpu/drm/i915/gt/intel_gt_mcr.c:256: +void intel_gt_mcr_multicast_write_fw(struct intel_gt *gt, + i915_reg_t reg, u32 value) total: 0 errors, 0 warnings, 2 checks, 585 lines checked f6a046f25e7a drm/i915/gt: Always use MCR functions on multicast registers 8b11a87b6b95 drm/i915/guc: Handle save/restore of MCR registers explicitly 5ddc6625b12c drm/i915/gt: Add MCR-specific workaround initializers -:104: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #104: FILE: drivers/gpu/drm/i915/gt/intel_workarounds.c:289: + wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); -:519: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #519: FILE: drivers/gpu/drm/i915/gt/intel_workarounds.c:2110: + wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX); -:553: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #553: FILE: drivers/gpu/drm/i915/gt/intel_workarounds.c:2143: + wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, GEN12_DISABLE_READ_SUPPRESSION); -:572: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #572: FILE: drivers/gpu/drm/i915/gt/intel_workarounds.c:2159: + wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, MDQ_ARBITRATION_MODE | UGM_BACKUP_MODE); total: 0 errors, 0 warnings, 4 checks, 745 lines checked 6c89ba18065f drm/i915: Define multicast registers as a new type -:605: WARNING:NEW_TYPEDEFS: do not add new typedefs #605: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:107: +typedef struct { total: 0 errors, 1 warnings, 0 checks, 506 lines checked 49afc6dca4e4 drm/i915/xehp: Eliminate shared/implicit steering
