On Tue, Mar 29, 2022 at 03:31:00PM -0700, José Roberto de Souza wrote:
> From: Caz Yokoyama <caz.yokoyama@xxxxxxxxx>
>
> Alderlake-P has different MBUS DBOX BW and B credits than other
> platforms, so here setting it properly.
Hmm. No explicit table for these so I guess we're going by the register
defaults here.
Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> BSpec: 49213
> BSpec: 50343
> Cc: Matt Roper <matthew.d.roper@xxxxxxxxx>
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@xxxxxxxxx>
> Cc: Jani Nikula <jani.nikula@xxxxxxxxx>
> Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> Signed-off-by: Caz Yokoyama <caz.yokoyama@xxxxxxxxx>
> Signed-off-by: José Roberto de Souza <jose.souza@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 234f363aad651..389a3c988dc6f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1844,7 +1844,10 @@ static void icl_pipe_mbus_enable(struct intel_crtc *crtc, bool joined_mbus)
> else
> val |= MBUS_DBOX_A_CREDIT(2);
>
> - if (DISPLAY_VER(dev_priv) >= 12) {
> + if (IS_ALDERLAKE_P(dev_priv)) {
> + val |= MBUS_DBOX_BW_CREDIT(2);
> + val |= MBUS_DBOX_B_CREDIT(8);
> + } else if (DISPLAY_VER(dev_priv) >= 12) {
> val |= MBUS_DBOX_BW_CREDIT(2);
> val |= MBUS_DBOX_B_CREDIT(12);
> } else {
> --
> 2.35.1
--
Ville Syrjälä
Intel
