== Series Details == Series: drm/i915: Start reordering modeset clock calculations (rev3) URL : https://patchwork.freedesktop.org/series/101789/ State : warning == Summary == $ dim checkpatch origin/drm-tip eef669f225cd drm/i915: Make .get_dplls() return int 526bd16336db drm/i915: Pass dev_priv to intel_shared_dpll_init() 657130d86c57 drm/i915: Remove pointless dpll_funcs checks d97da58c081b drm/i915: Adjust .crtc_compute_clock() calling convention 8229e8880231 drm/i915: Move stuff into intel_dpll_crtc_compute_clock() fc05b45e8924 drm/i915: Move the dpll_hw_state clearing to intel_dpll_crtc_compute_clock() afcd83860b16 drm/i915: Clear the dpll_hw_state when disabling a pipe 871f0d8b7c92 drm/i915: Split out dg2_crtc_compute_clock() 2ebb495949cc drm/i915: Add crtc .crtc_get_shared_dpll() 1d067b0daf49 drm/i915: Split shared dpll .get_dplls() into compute and get phases -:191: CHECK:CAMELCASE: Avoid CamelCase: <SPLL_FREQ_1350MHz> #191: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:1063: + SPLL_PLL_ENABLE | SPLL_FREQ_1350MHz | SPLL_REF_MUXED_SSC; total: 0 errors, 0 warnings, 1 checks, 516 lines checked f52d29ef90c2 drm/i915: Do .crtc_compute_clock() earlier 282084c82d01 drm/i915: Clean up DPLL related debugs 0c8cf5704839 drm/i915: Reassign DPLLs only for crtcs going throug .compute_config()
