On Mon, Mar 28, 2022 at 12:16:15PM -0700, José Roberto de Souza wrote:
> From: Caz Yokoyama <caz.yokoyama@xxxxxxxxx>
>
> B credits set by IFWI do not match with specification default, so here
> programming the right value.
>
> Also while at it, taking the oportunity to do a read-modify-write to
> not overwrite all other bits in this register that specification don't
> ask us to change.
RMWs considered harmful. This is a double buffered register and in the
future we may have to program it via DSB to update it atomically with
the rest of the registers (eg. if we want to avoid the modeset for the
mbus joining change). And when that happens the RMW will have to be
removed again since the DSB can't even read registers. So IMO better
to not even start down this path.
>
> BSpec: 49213
> BSpec: 50343
> Cc: Matt Roper <matthew.d.roper@xxxxxxxxx>
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@xxxxxxxxx>
> Cc: Jani Nikula <jani.nikula@xxxxxxxxx>
> Signed-off-by: Caz Yokoyama <caz.yokoyama@xxxxxxxxx>
> Signed-off-by: José Roberto de Souza <jose.souza@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 12 +++++++++---
> 1 file changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 3d2ff258f0a94..078ada041e1cd 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1830,13 +1830,19 @@ static void icl_pipe_mbus_enable(struct intel_crtc *crtc, bool joined_mbus)
> enum pipe pipe = crtc->pipe;
> u32 val;
>
> + val = intel_de_read(dev_priv, PIPE_MBUS_DBOX_CTL(pipe));
> + val &= ~MBUS_DBOX_A_CREDIT_MASK;
> /* Wa_22010947358:adl-p */
> if (IS_ALDERLAKE_P(dev_priv))
> - val = joined_mbus ? MBUS_DBOX_A_CREDIT(6) : MBUS_DBOX_A_CREDIT(4);
> + val |= joined_mbus ? MBUS_DBOX_A_CREDIT(6) : MBUS_DBOX_A_CREDIT(4);
> else
> - val = MBUS_DBOX_A_CREDIT(2);
> + val |= MBUS_DBOX_A_CREDIT(2);
>
> - if (DISPLAY_VER(dev_priv) >= 12) {
> + val &= ~(MBUS_DBOX_BW_CREDIT_MASK | MBUS_DBOX_B_CREDIT_MASK);
> + if (IS_ALDERLAKE_P(dev_priv)) {
> + val |= MBUS_DBOX_BW_CREDIT(2);
> + val |= MBUS_DBOX_B_CREDIT(8);
> + } else if (DISPLAY_VER(dev_priv) >= 12) {
> val |= MBUS_DBOX_BW_CREDIT(2);
> val |= MBUS_DBOX_B_CREDIT(12);
> } else {
> --
> 2.35.1
--
Ville Syrjälä
Intel
