On Fri, 2022-03-18 at 05:22 -0700, José Roberto de Souza wrote:
> On Fri, 2022-03-18 at 10:52 +0200, Stanislav Lisovskiy wrote:
> > We are currently getting FIFO underruns, in particular
> > when PSR2 is enabled. There seem to be no existing workaround
> > or patches, which can fix that issue(were expecting some recent
> > selective fetch update and DBuf bw/SAGV fixes to help,
> > which unfortunately didn't).
> > Current idea is that it looks like for some reason the
> > DBuf prefill time isn't enough once we exit PSR2, despite its
> > theoretically correct.
> > So bump it up a bit by 15%(minimum experimental amount required
> > to get it working), if PSR2 is enabled.
> > For PSR1 there is no need in this hack, so we limit it only
> > to PSR2 and Alderlake.
>
> It this workaround meant to be permanent? If yes we should file a HSD and get hardware folks feedback.
>
> >
> > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@xxxxxxxxx>
> > ---
> > drivers/gpu/drm/i915/display/intel_cdclk.c | 13 +++++++++++++
> > 1 file changed, 13 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > index 8888fda8b701..095b79950788 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > @@ -2325,6 +2325,19 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
> > dev_priv->max_cdclk_freq));
> > }
> >
>
> Please add some comment in the code about this workaround.
>
>
> > + if (IS_ALDERLAKE_P(dev_priv)) {
> > + struct intel_encoder *encoder;
> > +
> > + for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
> > + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > +
> > + if (intel_dp->psr.psr2_enabled) {
>
> You should check the has_psr2 in the crtc_state, PSR2 could be disabled when this state is committed.
Ah and if a remember correctly those underruns only happens in a scenario with 4 pipes enabled? or it also happens with 2 and 3 pipes?
Anyways would be better to narrow down the cases where the workaround is applied.
So for at least in a case with a single pipe enabled we can have the lowest cdclk as possible.
>
> > + min_cdclk = DIV_ROUND_UP(min_cdclk * 100, 85);
>
> This is not increasing by 15%.
>
> min_cdclk = 500
> 500 * 100 = 50000
> 50000 / 85 = 588.235294118
>
> While 15% of 500 is 75.
>
> Also if there is two CRTCs with PSR2 enabled you will bump min_cdclk twice.
>
> > + break;
> > + }
> > + }
> > + }
> > +
> > if (min_cdclk > dev_priv->max_cdclk_freq) {
> > drm_dbg_kms(&dev_priv->drm,
> > "required cdclk (%d kHz) exceeds max (%d kHz)\n",
>
