On Wed, Mar 09, 2022 at 06:49:48PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> Name all the ICL_PCODE_SAGV_DE_MEM_SS_CONFIG request/response
> bits in a manner that we can actually understand what they're
> doing.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_bw.c | 9 +++++----
> drivers/gpu/drm/i915/i915_reg.h | 18 ++++++++++++------
> 2 files changed, 17 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index b794545ff81d..395e48930b08 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -124,8 +124,8 @@ int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
> /* bspec says to keep retrying for at least 1 ms */
> ret = skl_pcode_request(dev_priv, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG,
> points_mask,
> - ICL_PCODE_POINTS_RESTRICTED_MASK,
> - ICL_PCODE_POINTS_RESTRICTED,
> + ICL_PCODE_REP_QGV_MASK | ADLS_PCODE_REP_PSF_MASK,
> + ICL_PCODE_REP_QGV_SAFE | ADLS_PCODE_REP_PSF_SAFE,
> 1);
>
> if (ret < 0) {
> @@ -833,7 +833,7 @@ static u16 icl_qgv_points_mask(struct drm_i915_private *i915)
> if (num_psf_gv_points > 0)
> psf_points = GENMASK(num_psf_gv_points - 1, 0);
>
> - return ADLS_QGV_PT(qgv_points) | ADLS_PSF_PT(psf_points);
> + return ICL_PCODE_REQ_QGV_PT(qgv_points) | ADLS_PCODE_REQ_PSF_PT(psf_points);
> }
>
> static int intel_bw_check_data_rate(struct intel_atomic_state *state, bool *changed)
> @@ -1000,7 +1000,8 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
> * actually accepts as a parameter.
> */
> new_bw_state->qgv_points_mask =
> - ~(ADLS_QGV_PT(qgv_points) | ADLS_PSF_PT(psf_points)) &
> + ~(ICL_PCODE_REQ_QGV_PT(qgv_points) |
> + ADLS_PCODE_REQ_PSF_PT(psf_points)) &
> icl_qgv_points_mask(dev_priv);
>
> /*
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 48a12f6c19b4..504499fad97d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6720,12 +6720,18 @@
> #define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8))
> #define ADL_PCODE_MEM_SS_READ_PSF_GV_INFO ((0) | (0x2 << 8))
> #define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe
> -#define ICL_PCODE_POINTS_RESTRICTED 0x0
> -#define ICL_PCODE_POINTS_RESTRICTED_MASK 0xf
> -#define ADLS_QGV_PT_MASK REG_GENMASK(7, 0)
> -#define ADLS_QGV_PT(x) REG_FIELD_PREP(ADLS_QGV_PT_MASK, (x))
> -#define ADLS_PSF_PT_MASK REG_GENMASK(10, 8)
> -#define ADLS_PSF_PT(x) REG_FIELD_PREP(ADLS_PSF_PT_MASK, (x))
> +#define ICL_PCODE_REP_QGV_MASK REG_GENMASK(1, 0)
> +#define ICL_PCODE_REP_QGV_SAFE REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 0)
> +#define ICL_PCODE_REP_QGV_POLL REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 1)
> +#define ICL_PCODE_REP_QGV_REJECTED REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 2)
> +#define ADLS_PCODE_REP_PSF_MASK REG_GENMASK(3, 2)
> +#define ADLS_PCODE_REP_PSF_SAFE REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 0)
> +#define ADLS_PCODE_REP_PSF_POLL REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 1)
> +#define ADLS_PCODE_REP_PSF_REJECTED REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 2)
> +#define ICL_PCODE_REQ_QGV_PT_MASK REG_GENMASK(7, 0)
> +#define ICL_PCODE_REQ_QGV_PT(x) REG_FIELD_PREP(ICL_PCODE_REQ_QGV_PT_MASK, (x))
> +#define ADLS_PCODE_REQ_PSF_PT_MASK REG_GENMASK(10, 8)
> +#define ADLS_PCODE_REQ_PSF_PT(x) REG_FIELD_PREP(ADLS_PCODE_REQ_PSF_PT_MASK, (x))
> #define GEN6_PCODE_READ_D_COMP 0x10
> #define GEN6_PCODE_WRITE_D_COMP 0x11
> #define ICL_PCODE_EXIT_TCCOLD 0x12
> --
> 2.34.1
>
