On Tue, 08 Mar 2022, Ville Syrjala <ville.syrjala@xxxxxxxxxxxxxxx> wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> struct dp_link_dpll is a pointless wrapper around struct dpll.
> Just store the desired link rate into struct dpll::dot and
> we're done.
>
> v2: Document the full divider as a proper decimal number on chv
> Nuke bogus eDP 1.4 comments for chv while at it
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Reviewed-by: Jani Nikula <jani.nikula@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/g4x_dp.c | 55 +++++++++------------------
> 1 file changed, 17 insertions(+), 38 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c
> index 22345051e667..8e1338678d91 100644
> --- a/drivers/gpu/drm/i915/display/g4x_dp.c
> +++ b/drivers/gpu/drm/i915/display/g4x_dp.c
> @@ -24,58 +24,37 @@
> #include "intel_pps.h"
> #include "vlv_sideband.h"
>
> -struct dp_link_dpll {
> - int clock;
> - struct dpll dpll;
> +static const struct dpll g4x_dpll[] = {
> + { .dot = 162000, .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8, },
> + { .dot = 270000, .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2, },
> };
>
> -static const struct dp_link_dpll g4x_dpll[] = {
> - { 162000,
> - { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
> - { 270000,
> - { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
> +static const struct dpll pch_dpll[] = {
> + { .dot = 162000, .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9, },
> + { .dot = 270000, .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8, },
> };
>
> -static const struct dp_link_dpll pch_dpll[] = {
> - { 162000,
> - { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
> - { 270000,
> - { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
> +static const struct dpll vlv_dpll[] = {
> + { .dot = 162000, .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81, },
> + { .dot = 270000, .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27, },
> };
>
> -static const struct dp_link_dpll vlv_dpll[] = {
> - { 162000,
> - { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
> - { 270000,
> - { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
> -};
> -
> -/*
> - * CHV supports eDP 1.4 that have more link rates.
> - * Below only provides the fixed rate but exclude variable rate.
> - */
> -static const struct dp_link_dpll chv_dpll[] = {
> - /*
> - * CHV requires to program fractional division for m2.
> - * m2 is stored in fixed point format using formula below
> - * (m2_int << 22) | m2_fraction
> - */
> - { 162000, /* m2_int = 32, m2_fraction = 1677722 */
> - { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
> - { 270000, /* m2_int = 27, m2_fraction = 0 */
> - { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
> +static const struct dpll chv_dpll[] = {
> + /* m2 is .22 binary fixed point */
> + { .dot = 162000, .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a /* 32.4 */ },
> + { .dot = 270000, .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 /* 27.0 */ },
> };
>
> const struct dpll *vlv_get_dpll(struct drm_i915_private *i915)
> {
> - return IS_CHERRYVIEW(i915) ? &chv_dpll[0].dpll : &vlv_dpll[0].dpll;
> + return IS_CHERRYVIEW(i915) ? &chv_dpll[0] : &vlv_dpll[0];
> }
>
> void g4x_dp_set_clock(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - const struct dp_link_dpll *divisor = NULL;
> + const struct dpll *divisor = NULL;
> int i, count = 0;
>
> if (IS_G4X(dev_priv)) {
> @@ -94,8 +73,8 @@ void g4x_dp_set_clock(struct intel_encoder *encoder,
>
> if (divisor && count) {
> for (i = 0; i < count; i++) {
> - if (pipe_config->port_clock == divisor[i].clock) {
> - pipe_config->dpll = divisor[i].dpll;
> + if (pipe_config->port_clock == divisor[i].dot) {
> + pipe_config->dpll = divisor[i];
> pipe_config->clock_set = true;
> break;
> }
--
Jani Nikula, Intel Open Source Graphics Center
