On Tue, 01 Mar 2022, Ville Syrjala <ville.syrjala@xxxxxxxxxxxxxxx> wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> bxt_clk_div is basically the same as struct dpll. Just use the latter.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Reviewed-by: Jani Nikula <jani.nikula@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 50 ++++++-------------
> 1 file changed, 16 insertions(+), 34 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 4a82e630cbec..58e9d5960bc6 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -2080,75 +2080,57 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
> return ret;
> }
>
> -/* bxt clock parameters */
> -struct bxt_clk_div {
> - int clock;
> - u32 p1;
> - u32 p2;
> - u32 m2;
> - u32 n;
> -
> - int vco;
> -};
> -
> /* pre-calculated values for DP linkrates */
> -static const struct bxt_clk_div bxt_dp_clk_val[] = {
> - { .clock = 162000, .p1 = 4, .p2 = 2, .n = 1,
> +static const struct dpll bxt_dp_clk_val[] = {
> + { .dot = 162000, .p1 = 4, .p2 = 2, .n = 1,
> .m2 = 0x819999a /* .m2_int = 32, m2_frac = 1677722 */ },
> - { .clock = 270000, .p1 = 4, .p2 = 1, .n = 1,
> + { .dot = 270000, .p1 = 4, .p2 = 1, .n = 1,
> .m2 = 0x6c00000 /* .m2_int = 27, m2_frac = 0 */ },
> - { .clock = 540000, .p1 = 2, .p2 = 1, .n = 1,
> + { .dot = 540000, .p1 = 2, .p2 = 1, .n = 1,
> .m2 = 0x6c00000 /* .m2_int = 27, m2_frac = 0 */ },
> - { .clock = 216000, .p1 = 3, .p2 = 2, .n = 1,
> + { .dot = 216000, .p1 = 3, .p2 = 2, .n = 1,
> .m2 = 0x819999a /* .m2_int = 32, m2_frac = 1677722 */ },
> - { .clock = 243000, .p1 = 4, .p2 = 1, .n = 1,
> + { .dot = 243000, .p1 = 4, .p2 = 1, .n = 1,
> .m2 = 0x6133333 /* .m2_int = 24, m2_frac = 1258291 */ },
> - { .clock = 324000, .p1 = 4, .p2 = 1, .n = 1,
> + { .dot = 324000, .p1 = 4, .p2 = 1, .n = 1,
> .m2 = 0x819999a /* .m2_int = 32, m2_frac = 1677722 */ },
> - { .clock = 432000, .p1 = 3, .p2 = 1, .n = 1,
> + { .dot = 432000, .p1 = 3, .p2 = 1, .n = 1,
> .m2 = 0x819999a /* .m2_int = 32, m2_frac = 1677722 */ },
> };
>
> static bool
> bxt_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state,
> - struct bxt_clk_div *clk_div)
> + struct dpll *clk_div)
> {
> struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - struct dpll best_clock;
>
> /* Calculate HDMI div */
> /*
> * FIXME: tie the following calculation into
> * i9xx_crtc_compute_clock
> */
> - if (!bxt_find_best_dpll(crtc_state, &best_clock)) {
> + if (!bxt_find_best_dpll(crtc_state, clk_div)) {
> drm_dbg(&i915->drm, "no PLL dividers found for clock %d pipe %c\n",
> crtc_state->port_clock,
> pipe_name(crtc->pipe));
> return false;
> }
>
> - clk_div->p1 = best_clock.p1;
> - clk_div->p2 = best_clock.p2;
> - drm_WARN_ON(&i915->drm, best_clock.m1 != 2);
> - clk_div->n = best_clock.n;
> - clk_div->m2 = best_clock.m2;
> -
> - clk_div->vco = best_clock.vco;
> + drm_WARN_ON(&i915->drm, clk_div->m1 != 2);
>
> return true;
> }
>
> static void bxt_ddi_dp_pll_dividers(struct intel_crtc_state *crtc_state,
> - struct bxt_clk_div *clk_div)
> + struct dpll *clk_div)
> {
> int clock = crtc_state->port_clock;
> int i;
>
> *clk_div = bxt_dp_clk_val[0];
> for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
> - if (bxt_dp_clk_val[i].clock == clock) {
> + if (bxt_dp_clk_val[i].dot == clock) {
> *clk_div = bxt_dp_clk_val[i];
> break;
> }
> @@ -2158,7 +2140,7 @@ static void bxt_ddi_dp_pll_dividers(struct intel_crtc_state *crtc_state,
> }
>
> static bool bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state,
> - const struct bxt_clk_div *clk_div)
> + const struct dpll *clk_div)
> {
> struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> struct intel_dpll_hw_state *dpll_hw_state = &crtc_state->dpll_hw_state;
> @@ -2230,7 +2212,7 @@ static bool bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state,
> static bool
> bxt_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
> {
> - struct bxt_clk_div clk_div = {};
> + struct dpll clk_div = {};
>
> bxt_ddi_dp_pll_dividers(crtc_state, &clk_div);
>
> @@ -2240,7 +2222,7 @@ bxt_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
> static bool
> bxt_ddi_hdmi_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
> {
> - struct bxt_clk_div clk_div = {};
> + struct dpll clk_div = {};
>
> bxt_ddi_hdmi_pll_dividers(crtc_state, &clk_div);
--
Jani Nikula, Intel Open Source Graphics Center
