On Tue, 01 Mar 2022, Ville Syrjala <ville.syrjala@xxxxxxxxxxxxxxx> wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> Toss a bunch if constants into .rodata drom the stack. Also
> shrink the types of some of the arrays to reduce the size.
>
> bloat-o-meter -c intel_dpll_mgr.o:
> add/remove: 0/0 grow/shrink: 0/2 up/down: 0/-86 (-86)
> Function old new delta
> icl_get_dplls 3393 3372 -21
> skl_get_dpll 2069 2004 -65
> Total: Before=28029, After=27943, chg -0.31%
> add/remove: 0/0 grow/shrink: 0/0 up/down: 0/0 (0)
> Data old new delta
> Total: Before=17, After=17, chg +0.00%
> add/remove: 2/0 grow/shrink: 0/2 up/down: 28/-129 (-101)
> RO Data old new delta
> dco_central_freq - 24 +24
> div1_vals - 4 +4
> odd_dividers 28 7 -21
> even_dividers 144 36 -108
> Total: Before=3600, After=3499, chg -2.81%
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Reviewed-by: Jani Nikula <jani.nikula@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 24 +++++++++----------
> 1 file changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 1b1b70f0ff93..4e06c8203aca 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -1495,18 +1495,17 @@ skl_ddi_calculate_wrpll(int clock /* in Hz */,
> int ref_clock,
> struct skl_wrpll_params *wrpll_params)
> {
> - u64 afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
> - u64 dco_central_freq[3] = { 8400000000ULL,
> - 9000000000ULL,
> - 9600000000ULL };
> - static const int even_dividers[] = { 4, 6, 8, 10, 12, 14, 16, 18, 20,
> - 24, 28, 30, 32, 36, 40, 42, 44,
> - 48, 52, 54, 56, 60, 64, 66, 68,
> - 70, 72, 76, 78, 80, 84, 88, 90,
> - 92, 96, 98 };
> - static const int odd_dividers[] = { 3, 5, 7, 9, 15, 21, 35 };
> + static const u64 dco_central_freq[3] = { 8400000000ULL,
> + 9000000000ULL,
> + 9600000000ULL };
> + static const u8 even_dividers[] = { 4, 6, 8, 10, 12, 14, 16, 18, 20,
> + 24, 28, 30, 32, 36, 40, 42, 44,
> + 48, 52, 54, 56, 60, 64, 66, 68,
> + 70, 72, 76, 78, 80, 84, 88, 90,
> + 92, 96, 98 };
> + static const u8 odd_dividers[] = { 3, 5, 7, 9, 15, 21, 35 };
> static const struct {
> - const int *list;
> + const u8 *list;
> int n_dividers;
> } dividers[] = {
> { even_dividers, ARRAY_SIZE(even_dividers) },
> @@ -1517,6 +1516,7 @@ skl_ddi_calculate_wrpll(int clock /* in Hz */,
> };
> unsigned int dco, d, i;
> unsigned int p0, p1, p2;
> + u64 afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
>
> for (d = 0; d < ARRAY_SIZE(dividers); d++) {
> for (dco = 0; dco < ARRAY_SIZE(dco_central_freq); dco++) {
> @@ -2751,8 +2751,8 @@ static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
> struct intel_dpll_hw_state *state,
> bool is_dkl)
> {
> + static const u8 div1_vals[] = { 7, 5, 3, 2 };
> u32 dco_min_freq, dco_max_freq;
> - int div1_vals[] = {7, 5, 3, 2};
> unsigned int i;
> int div2;
--
Jani Nikula, Intel Open Source Graphics Center
