== Series Details == Series: i915: Prepare for Xe_HP compute engines URL : https://patchwork.freedesktop.org/series/100833/ State : warning == Summary == $ dim checkpatch origin/drm-tip aeab2e429058 drm/i915/xehp: Define compute class and engine 794deed65cd5 drm/i915/xehp: CCS shares the render reset domain 83e3525cfb56 drm/i915/xehp: Add Compute CS IRQ handlers c1e9139a6d18 drm/i915/xehp: compute engine pipe_control -:97: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV) #97: FILE: drivers/gpu/drm/i915/gt/intel_gpu_commands.h:231: +#define PIPE_CONTROL_AMFS_FLUSH (1<<25) /* gen12+ */ ^ -:102: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV) #102: FILE: drivers/gpu/drm/i915/gt/intel_gpu_commands.h:236: +#define PIPE_CONTROL_GLOBAL_SNAPSHOT_RESET (1<<19) ^ -:104: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV) #104: FILE: drivers/gpu/drm/i915/gt/intel_gpu_commands.h:238: +#define PIPE_CONTROL_PSD_SYNC (1<<17) /* gen11+ */ ^ total: 0 errors, 0 warnings, 3 checks, 95 lines checked 25857870fcd9 drm/i915/xehp: CCS should use RCS setup functions 4644209c10d6 drm/i915: Move context descriptor fields to intel_lrc.h a384c36be225 drm/i915/xehp: Define context scheduling attributes in lrc descriptor 4060c5ce8fe7 drm/i915/xehp/guc: enable compute engine inside GuC 8c2a3081039e drm/i915/xehp: Enable ccs/dual-ctx in RCU_MODE dee0a41826f5 drm/i915/xehp: Don't support parallel submission on compute / render -:44: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional statements (16, 23) #44: FILE: drivers/gpu/drm/i915/gt/uc/selftest_guc_multi_lrc.c:158: + if (class == COMPUTE_CLASS || class == RENDER_CLASS) + continue; -:45: WARNING:TABSTOP: Statements should start on a tabstop #45: FILE: drivers/gpu/drm/i915/gt/uc/selftest_guc_multi_lrc.c:159: + continue; total: 0 errors, 2 warnings, 0 checks, 26 lines checked e2d994ffd124 drm/i915/xehp: handle fused off CCS engines -:46: CHECK:OPEN_ENDED_LINE: Lines should not end with a '(' #46: FILE: drivers/gpu/drm/i915/gt/intel_engine_cs.c:607: + const unsigned long ccs_mask = intel_slicemask_from_dssmask( total: 0 errors, 0 warnings, 1 checks, 80 lines checked 2ea92310ad16 drm/i915/xehp: Add compute workarounds -:51: WARNING:LONG_LINE: line length of 102 exceeds 100 columns #51: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:1224: + cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE, 0); total: 0 errors, 1 warnings, 0 checks, 84 lines checked 1d7e9a4c4f20 drm/i915/xehpsdv: Move render/compute engine reset domains related workarounds
